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HIGFET and method

Assignee: NXP USA Inc
•
Filing: 1995-06-02
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Granted: 1997-03-25
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Expires: 2015-06-02
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Abstract

Abstract A HIGFET (10) utilizes an etch stop layer (17) to form a gate insulator (16) to be narrower than the gate electrode (21). This T-shaped gate structure facilitates forming source (23) and drain (24) regions that are separated from the gate insulator (16) by a distance (22) in order to reduce leakage current and increase the breakdown voltage.

Inventors

  • 👤 Jonathan K. Abrokwah
  • 👤 Rodolfo Lucero
  • 👤 Jeffrey A. Rollman

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-09 02:48
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/015; H10D30/40; H10D30/47; H10D30/80; H10D30/801; H10D62/00; H10D62/10; H10D62/13; H10D62/149; H10D62/151; H10D62/156; H10D62/157; H10P; H10P50/00; H10P50/73; H10P76/00; H10P76/40; H10P76/408; H10P76/4088; H10W; H10W20/00; H10W20/01; H10W20/071; H10W20/074

Claims Analysis

Total Claims: 8
Claim 1
Independent Claim 84 words
A HIGFET comprising: a III-V substrate having a channel layer; a T-shaped gate structure having a cross-member supported by a base, the base having an insulator positioned on a first etch stop layer in the substrate, and a second etch stop layer on the insulator, wherein the base has a width that is less than a width of the cross-member; and a doped region in the substrate wherein an edge of the doped region is a first distance from an edge of the insulator.
Claim 2
Dependent Claim 84 words
A HIGFET comprising: a III-V substrate having a channel layer; a T-shaped gate structure having a cross-member supported by a base, the base having an insulator positioned on a first etch stop layer in the substrate, and a second etch stop layer on the insulator, wherein the base has a width that is less than a width of the cross-member; and a doped region in the substrate wherein an edge of the doped region is a first distance from an edge of the insulator.
Claim 3
Dependent Claim 14 words
The HIGFET of claim 1 wherein the insulator does not overlay the doped region.
Claim 4
Dependent Claim 17 words
The HIGFET of claim 1 wherein the insulator has an aluminum arsenide content of at least 50%.
Claim 5
Dependent Claim 18 words
The HIGFET of claim 3 wherein the insulator is one of aluminum gallium arsenide or aluminum indium arsenide.
Claim 6
Dependent Claim 27 words
The HIGFET of claim 1 wherein the first etch stop layer is substantially intrinsic gallium arsenide and the second etch stop layer is substantially intrinsic aluminum arsenide.
Claim 7
Dependent Claim 15 words
The HIGFET of claim 1 wherein the first distance is approximately 50 to 1000 angstroms.
Claim 8
Dependent Claim 24 words
The HIGFET of claim 1 wherein the channel layer includes a layer of substantially intrinsic gallium arsenide on a layer of indium gallium arsenide.

References Cited (Backward Citations)

JPS604268A Cited
US4916498A Cited
JPH01170051A Cited
US5514891A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2000-03-24 2000-09-23 2001-03-25 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2004-03-24 2004-09-23 2005-03-25 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2008-03-24 2008-09-23 2009-03-25 $7700.00 Window Closed / Lapsed

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