Method of making a multilayer LTCC tub architecture for hermetically sealing semiconductor die, external electrical access for which is provided by way of sidewall recesses

Claim 1

A method of manufacturing a packaging device for a semiconductor circuit chip, comprising the steps of: (a) providing a plurality of dielectric layers of preselected shapes; (b) forming prescribed patterns of vias in said dielectric layers; (c) providing conductive material in selected ones of the vias of said prescribed patterns of vias in said dielectric layers and electrical interconnect patterns intersecting selected vias on surfaces of selected ones of said layers; (d) laminating a stack of the layers processed in step (c), so as to form a tub-configured structure having a floor member upon which a semiconductor circuit chip is mountable, and a wall member surrounding and adjoining said floor member, said wall member having an inner wall member portion adjacent to a mounting surface portion of said floor member upon which a semiconductor circuit chip is mountable, extending a first height above said floor member, and an outer wall member portion adjoining said inner wall member and extending a second height above said floor member, greater than said first height, and wherein a portion of the electrical interconnect patterns formed in step (c) on said inner wall member portion has one or more first contact regions formed on a first, top surface portion thereof, so that said one or more first contact regions may be electrically connectable to a semiconductor circuit chip mounted on the adjacent mounting surface region of said floor member, and said electrical interconnect patterns include an electrical interconnection network which extends between said one or more first contact regions and one or more second and third contact regions defined by respective conductive vias; and (e) removing material from the layers of said stack so as to expose said second and third contact regions, and form one or more conductive first pockets at a top surface of an outer sidewall edge of said outer wall portion, and one or more conductive second pockets at a bottom surface of said outer sidewall edge of said outer wall portion.

Claim 2

A method of manufacturing a packaging device for a semiconductor circuit chip, comprising the steps of: (a) providing a plurality of dielectric layers of preselected shapes; (b) forming prescribed patterns of vias in said dielectric layers; (c) providing conductive material in selected ones of the vias of said prescribed patterns of vias in said dielectric layers and electrical interconnect patterns intersecting selected vias on surfaces of selected ones of said layers; (d) laminating a stack of the layers processed in step (c), so as to form a tub-configured structure having a floor member upon which a semiconductor circuit chip is mountable, and a wall member surrounding and adjoining said floor member, said wall member having an inner wall member portion adjacent to a mounting surface portion of said floor member upon which a semiconductor circuit chip is mountable, extending a first height above said floor member, and an outer wall member portion adjoining said inner wall member and extending a second height above said floor member, greater than said first height, and wherein a portion of the electrical interconnect patterns formed in step (c) on said inner wall member portion has one or more first contact regions formed on a first, top surface portion thereof, so that said one or more first contact regions may be electrically connectable to a semiconductor circuit chip mounted on the adjacent mounting surface region of said floor member, and said electrical interconnect patterns include an electrical interconnection network which extends between said one or more first contact regions and one or more second and third contact regions defined by respective conductive vias; and (e) removing material from the layers of said stack so as to expose said second and third contact regions, and form one or more conductive first pockets at a top surface of an outer sidewall edge of said outer wall portion, and one or more conductive second pockets at a bottom surface of said outer sidewall edge of said outer wall portion.