Method for handling instructions from a branch prior to instruction decoding in a computer which executes variable-length instructions

Claim 1

In a computer which executes variable-length instructions, and includes first and second buffers for storage of instructions provided from a memory, a bypass bus coupled to the memory that bypasses the first and second instruction buffers, a multiplexer configured to select between the first and second instruction buffers and the bypass bus, a rotator coupled to the multiplexer, an instruction decoder coupled to the rotator, and instruction buffer logic for control thereof, a method of handling instructions from a branch comprising the steps of: (a) flushing instructions of an initial instruction stream from the first and second instruction buffers responsive to a flush signal generated by the instruction buffer logic; (b) loading the first instruction buffer with a first block of instructions of a target instruction stream specified by the branch; (c) providing instruction bytes to the rotator via the bypass bus; (d) initializing a pointer generated by the instruction buffer logic to point to a byte location in the first block of instructions associated with a first valid instruction of the target instruction stream; (e) loading a next block of instructions of the target instruction stream into the second instruction buffer; (f) alternately selecting by the multiplexer instructions of the target instruction stream from the first and second instruction buffers for input to the rotator; (g) rotating by the rotator the instructions provided by the multiplexer in accordance with the pointer to align the instructions on boundaries.