Ferroelectric memory automatically generating biasing pulse for plate electrode

Claim 1

A ferroelectric memory which has a plurality of memory cells arranged in rows and columns, each column comprising a bit line connected to said memory cells along the column, each said memory cell comprising a ferroelectric capacitor having first and second electrodes, the polarization of said capacitors indicating to the status of data stored therewithin, the improvement wherein: said memory further comprises a plurality of word lines and a plurality of plate lines distinct from said bit lines and word lines, each of the memory cells provided along a row being connected to a word line corresponding to the row, each memory cell being also connected to a corresponding plate line, each plate line being connected to plate electrodes in a plurality of said memory cells, each said memory cell further including a respective switching device, said first electrode of said capacitor in said memory cell being connected to its corresponding bit line through said switching device, said switching device being connected to be controlled by said corresponding word line, said second electrode of said capacitor in said cell being connected to said corresponding plate line, said memory further comprising a plurality of pulse generators, each provided between each word line and each plate line of each row, said each pulse generator controlled by said each word line.