Patent US5608348A successfully refreshed from Google Patents.
US5608348A
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Binary programmable current mirror
Assignee: Delphi Technologies Inc
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Filing: 1996-05-22
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Granted: 1997-03-04
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Expires: 2016-05-22
Abstract
Abstract A programmable current mirror circuit suitable for incorporation into circuit designs and programmably tailored to produce a ratio of current output over current input based upon the status of a plurality of binary weighted switches. The resulting circuit is readily tailored so as to be insensitive to the "on" characteristics of the switches. Alternatively, the switches may comprise transistors controlled by accompanying circuitry operable to produce an equivalent switching function. An input current divider circuit network formed from an array of current mirrors fractionally divides an input current into a plurality of equivalent currents. A binary weighting circuit receives such fractional input currents, and applies a binary weight to each of same. A voltage to current converter receives the binary weighted voltage and converts the voltage to a weighted output current proportional to the input current directly in relation to the binary weighting applied via the binary weighting circuit.
Inventors
- 👤 Mark B. Kearney
- 👤 Douglas B. Osborn
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 15:40
CPC Classifications
G; G05; G05F; G05F3/00; G05F3/02; G05F3/08; G05F3/10; G05F3/16; G05F3/20; G05F3/26; G05F3/265
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
171 words
A programmable current mirror circuit comprising: an input terminal configured for receiving an analog input current; an input current divider circuit configured to receive the input current and divide the input current into a plurality of fractional source currents each being substantially identical; a binary weighting circuit configured to receive one or more of the fractional source currents and provide an associated weighted voltage; a plurality of switches each configured to ground out one of the fractional source currents when enabled so as to prevent current flow to said binary weighting circuit from said respective fractional source current; a plurality of forward current flow circuit means each configured to prevent reverse current flow from said binary weighting circuit to said switches and coupling the fractional source currents to said binary weighting circuit for imparting a binary weighting thereto; and voltage to current converting means configured to receive the binary weighting voltage, said converting circuit means converting said binary weighted voltage to a weighted output current proportional to the binary weighted voltage.
Claim 2
Dependent Claim
171 words
A programmable current mirror circuit comprising: an input terminal configured for receiving an analog input current; an input current divider circuit configured to receive the input current and divide the input current into a plurality of fractional source currents each being substantially identical; a binary weighting circuit configured to receive one or more of the fractional source currents and provide an associated weighted voltage; a plurality of switches each configured to ground out one of the fractional source currents when enabled so as to prevent current flow to said binary weighting circuit from said respective fractional source current; a plurality of forward current flow circuit means each configured to prevent reverse current flow from said binary weighting circuit to said switches and coupling the fractional source currents to said binary weighting circuit for imparting a binary weighting thereto; and voltage to current converting means configured to receive the binary weighting voltage, said converting circuit means converting said binary weighted voltage to a weighted output current proportional to the binary weighted voltage.
Claim 3
Dependent Claim
79 words
The programmable current mirror circuit as defined in claim 1 wherein said input current divider circuit comprises a plurality of transistors, each with a first and second terminal defining a current path and a control terminal, said first terminal connected to a resistor that is further connected to said circuit input terminal, said second terminal being connected to a respective reference terminal providing the corresponding fractionally source current, and said control terminal being connected to a voltage bias terminal.
Claim 4
Dependent Claim
52 words
The programmable current mirror circuit as defined in claim 1 wherein said input current divider circuit comprises an array of four substantially identical resistors and four substantially identical transistors configured so as to provide four references, each provided from one of the transistor second terminals as one of the fractional source currents.
Claim 5
Dependent Claim
72 words
The programmable current mirror circuit as defined in claim 1 wherein each of said switches includes a first and a second terminal defining an interruptible current path, said first terminal connected to a respective one of said fractional source currents, and said second terminal connected to a ground, said switch electrically grounding-out current flow from the respective source current when said switch is enabled so as to provide the interruptible current path.
Claim 6
Dependent Claim
40 words
The programmable current mirror circuit as defined in claim 1 wherein said plurality of forward current flow circuit means comprise a plurality of forward current flow diodes configured such that one of said diodes receives a respective fractional source current.
Claim 7
Dependent Claim
50 words
The programmable current mirror circuit as defined in claim 1 wherein said binary weighting circuit comprises an R-2R ladder network configured to receive current output from an associated terminal from said forward current flow circuit means so as to provide the associated binary weighted voltage at a voltage output terminal.
Claim 8
Dependent Claim
103 words
The programmable current mirror circuit as defined in claim 1 wherein said voltage to current converting circuit means comprises: an operational amplifier configured to receive the weighted voltage from said binary weighting circuit at a positive input terminal and connected at an output to a transistor; a resistor serially connected to the transistor, and a current output terminal connected with said transistor, wherein said voltage to current converting circuit means drive an upward current at said current output terminal in relation to an input current at said input terminal as determined by a binary code controlling the status of said plurality of switches.
Claim 9
Dependent Claim
17 words
The programmable current mirror circuit as defined in claim 7 wherein said transistor comprises a Darlington transistor.
Claim 10
Dependent Claim
181 words
A programmable current mirror circuit comprising: an input terminal for receiving an input current; a current divider network configured to receive the input current from said input terminal and divide the input current into four substantially identical fractional source currents each divided at a respective network terminal; a binary weighting circuit configured to receive the fractional source currents from said current divider network; a plurality of switches each configured to ground out one of the fractional input currents when enabled so as to shunt current flow to said binary weighting circuit via a respective one of said network terminals; forward current flow circuit means configured for ensuring a forward flow of current from said input current divider circuit to said binary weighting circuit and for preventing reverse current flow from the binary weighting circuit to said switches; and voltage to current converting circuit means configured to receive a binary weighted voltage from said binary weighting circuit, said voltage to current converting circuit means operable to convert the binary weighted voltage to a weighted output current proportional to such binary weighted voltage.
Claim 11
Dependent Claim
181 words
A programmable current mirror circuit comprising: an input terminal for receiving an input current; a current divider network configured to receive the input current from said input terminal and divide the input current into four substantially identical fractional source currents each divided at a respective network terminal; a binary weighting circuit configured to receive the fractional source currents from said current divider network; a plurality of switches each configured to ground out one of the fractional input currents when enabled so as to shunt current flow to said binary weighting circuit via a respective one of said network terminals; forward current flow circuit means configured for ensuring a forward flow of current from said input current divider circuit to said binary weighting circuit and for preventing reverse current flow from the binary weighting circuit to said switches; and voltage to current converting circuit means configured to receive a binary weighted voltage from said binary weighting circuit, said voltage to current converting circuit means operable to convert the binary weighted voltage to a weighted output current proportional to such binary weighted voltage.
Claim 12
Dependent Claim
36 words
The programmable current mirror circuit as defined in claim 9 wherein said current divider network comprises the four current sources configured to receive the input current and provide a plurality of substantially identical fractional input currents.
Claim 13
Dependent Claim
50 words
The programmable current mirror circuit as defined in claim 9 wherein said binary weighting circuit comprises an R-2R ladder network configured to receive current output from an associated terminal from said forward current flow circuit means so as to provide the associated binary weighted voltage at a voltage output terminal.
Claim 14
Independent Claim
129 words
A method of configuring an output current in relation to a specific input current, said method comprising the steps of: receiving an input current; dividing the input current into a plurality of substantially identical fractional currents; configuring a binary weighting circuit to receive anywhere from none to all of said fractional currents via current transmission controlled by a plurality of switches; grounding out any of said fractional source currents so as to prevent current flow to said binary weighting circuit; weighting, with said binary weighting circuit, the fractional source currents received thereby to provide associated binary weighted outputs and outputting a voltage dependent upon the binary weighted outputs received via said fractional currents; converting such voltage into an output current; and outputting such output current to an output terminal.
Claim 15
Independent Claim
129 words
A method of configuring an output current in relation to a specific input current, said method comprising the steps of: receiving an input current; dividing the input current into a plurality of substantially identical fractional currents; configuring a binary weighting circuit to receive anywhere from none to all of said fractional currents via current transmission controlled by a plurality of switches; grounding out any of said fractional source currents so as to prevent current flow to said binary weighting circuit; weighting, with said binary weighting circuit, the fractional source currents received thereby to provide associated binary weighted outputs and outputting a voltage dependent upon the binary weighted outputs received via said fractional currents; converting such voltage into an output current; and outputting such output current to an output terminal.
Claim 16
Dependent Claim
43 words
The method of claim 12 wherein the step of configuring the binary weighting circuit to receive said fractional currents further comprises the step of disabling a respective switch so as to interrupt a shunt to ground and provide a source of current therefrom.
Claim 17
Dependent Claim
118 words
A programmable current mirror circuit comprising: an input for receiving an analog input current; a current divider circuit configured to receive the input current and divide the input current into a plurality of fractional source currents; a binary weighting circuit configured to receive one or more of the fractional source currents and provide associated weighted voltages; a plurality of switches each configured to ground out one of the source currents when enabled so as to prevent current flow to said binary weighting circuit from the respective current source; and voltage to current converting means configured to receive the binary weighting voltage and convert said binary weighted voltage to a weighted output current proportional to the binary weighted voltage.
Claim 18
Dependent Claim
118 words
A programmable current mirror circuit comprising: an input for receiving an analog input current; a current divider circuit configured to receive the input current and divide the input current into a plurality of fractional source currents; a binary weighting circuit configured to receive one or more of the fractional source currents and provide associated weighted voltages; a plurality of switches each configured to ground out one of the source currents when enabled so as to prevent current flow to said binary weighting circuit from the respective current source; and voltage to current converting means configured to receive the binary weighting voltage and convert said binary weighted voltage to a weighted output current proportional to the binary weighted voltage.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-03-03 | 2000-09-02 | 2001-03-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-03-03 | 2004-09-02 | 2005-03-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-03-03 | 2008-09-02 | 2009-03-04 | $7700.00 | Window Closed / Lapsed |