Digital to analog converter with binary and binary coded decimal modes

Claim 2

A digital to analog converter (DAC) adapted to receive digital input signals and to produce an output analog signal corresponding to the digital input, said converter comprising a plurality of bit circuits arranged in progressive binary order, bias circuitry for said bit circuits, and means for converting from a binary to a BCD input mode, said converting means comprising, for each of a plurality of selected bit circuits, a selectable area-scaled transistor means internal to said DAC for increasing to a BCD level the individual output current of said selected bit circuits.

Claim 3

The DAC of claim 1, wherein each bit circuit includes a primary transistor means adapted for binary mode operation, each selected bit circuit includes a supplemental transistor means adapted to produce a supplemental output current which, together with the output current from the primary transistor means for said bit, is at a BCD level, and said bias circuitry provides a common bias for said primary and supplemental transistor means in the BCD mode, and further including means for switching each of said supplemental transistor means on or off for operation in BCD and binary modes respectively.

Claim 4

The DAC of claim 2, wherein the primary and supplemental transistor means for at least some of said selected bit circuits comprise a multiple emitter transistor having one emitter connected to provide a primary binary output current, and another emitter connected to provide a supplemental BCD output current.

Claim 5

The DAC of claim 2, said switching means comprising first means for actuating said primary transistor means, second means for actuating both said primary and supplemental transistor means, and means for switching between said first and second actuating means.

Claim 6

The DAC of claim 4, said first actuating means comprising a first bias circuit adapted to provide a reference bias current for said primary transistor means, said second actuating means comprising a second bias circuit adapted to provide a common reference bias current for the combination of said primary and supplemental transistor means, said second bias circuit being connected in circuit with said supplemental transistor means to enable the flow of supplemental output current under the control of said second actuating means.

Claim 7

The DAC of claim 1, wherein said bit circuits are arranged in functional groupings of four bit quads, said selected bit circuits comprising the bit circuits in the higher than first order quads.

Claim 8

The DAC of claim 6, said current increasing means comprising means to increase the output current of the bit circuits in each of said higher order quads by a compound factor of substantially 1.6 for each successive quad.

Claim 9

In a DAC arrangement having a plurality of bit circuits arranged in progressive binary order, bias circuitry for said bit circuits, and means for converting said DAC from a binary to a BCD mode, the improvement comprising means for substantially equalizing the full-scale binary mode output current with the full-scale BCD mode output current, said equalizing means comprising selectable means internal to said DAC and actuable in conjunction with said conversion means for amplifying, by a common amplification factor, the magnitudes of the BCD output currents for each bit circuit to amplified BCD levels sufficient to substantially equalize the full-scale binary mode and BCD mode output currents.

Claim 10

In a DAC arrangement having a plurality of bit circuits arranged in progressive binary order, bias circuitry for said bit circuits, and means for converting said DAC from a binary to a BCD mode, the improvement comprising means for substantially equalizing the full-scale binary mode output current with the full-scale BCD mode output current, said equalizing means comprising selectable means internal to said DAC and actuable in conjunction with said conversion means for amplifying, by a common amplification factor, the magnitudes of the BCD output currents for each bit circuit to amplified BCD levels sufficient to substantially equalize the full-scale binary mode and BCD mode output currents.

Claim 11

The DAC of claim 8, each of said bit circuits including transistor means controlling their output currents, wherein said current amplifying means comprises means for adjusting the bias signal for said bit transistor means.

Claim 12

The DAC of claim 9, said bias circuitry including a binary mode bias circuit, a BCD mode bias circuit, and switch means for selectively enabling one and disabling the other of said bias circuits.

Claim 13

The DAC of claim 10, wherein each bit circuit includes a primary transistor means adapted for binary mode operation, selected higher than first order bit circuits each include a supplemental transistor means adapted to produce a supplemental output current sufficient to bring the total bit circuit output current to a BCD level, said binary and BCD bias circuits each include reference current means adapted to direct a reference current through respective bias resistance means and thereby produce respective bias voltages, and said supplemental transistor means are connected for their currents to add to the BCD reference current and thereby increase the bias voltage during BCD mode operation.

Claim 14

The DAC of claim 11, and further including current source means connected in circuit with said supplemental transistor means to add to the current directed through said BCD bias resistor, the magnitude of the current produced by said current source means being sufficient to increase the BCD bias voltage to a level at which the full-scale binary and BCD output current levels are substantially equal.

Claim 15

A DAC comprising a plurality of bit circuits arranged in progressive binary order, bias circuit means for said bit circuits, a plurality of selectable transistor means internal to said DAC and actuable to increase the output current of selected higher than first order bit circuits to a BCD level, and means internal to said DAC and actuable in conjunction with actuation of said selectable transistor means for amplifying, by a common amplification factor, the magnitudes of the BCD output currents for each bit circuit to amplified BCD levels sufficient to equalize the full-scale binary mode and BCD mode output currents.

Claim 16

A DAC comprising a plurality of bit circuits arranged in progressive binary order, bias circuit means for said bit circuits, a plurality of selectable transistor means internal to said DAC and actuable to increase the output current of selected higher than first order bit circuits to a BCD level, and means internal to said DAC and actuable in conjunction with actuation of said selectable transistor means for amplifying, by a common amplification factor, the magnitudes of the BCD output currents for each bit circuit to amplified BCD levels sufficient to equalize the full-scale binary mode and BCD mode output currents.

Claim 17

The DAC of claim 13, each bit circuit including a primary transistor means adapted to produce a binary mode output current, the selectable transistor means for each selected bit circuit comprising a supplemental transistor means actuable to produce a supplemental output current sufficient to increase the total output current for its respective bit circuit to a BCD level, and further including switch means for actuating and deactuating each of said supplemental transistor means during BCD and binary mode operation, respectively.

Claim 18

The DAC of claim 14, said bias circuit means comprising a binary bias portion for said primary transistor means, a BCD bias portion for said primary and supplemental transistor means, and means for selectably enabling one of said bias circuit portions and disabling the other, said supplemental BCD transistor means being connected in circuit with said bias circuit means for actuation when said BCD bias portion is enabled.

Claim 19

The DAC of claim 15, said binary and BCD bias circuit portions including means for directing reference currents through binary and BCD bias resistors to establish respective bias voltages, said supplemental BCD transistor means being connected to add to the reference current applied through said BCD bias resistor.

Claim 20

The DAC of claim 16, said amplifying means comprising a current source means adapted to add to the supplemental transistor current directed through said BCD bias resistor, the magnitude of the current produced by said current source means being sufficient to increase the BCD bias voltage to a level at which the full-scale binary and BCD output current levels are substantially equal.

Claim 21

A digital to analog converter comprising a plurality of bit circuits arranged in a resistance ladder of progressive binary order and functionally grouped into four-bit quads, each bit circuit including a primary transistor means adapted to draw a predetermined amount of output current when its associated bit circuit is actuated, a transistor bias circuit for said bit circuits, and means for selecting between binary and BCD operation modes, said means comprising: for each transistor means of each bit circuit in the higher than first order quads, an associated area-scaled supplemental transistor means internal to said DAC, each of said supplemental transistor means being actuable to draw a supplemental output current of sufficient magnitude to establish a BCD relationship between the total of the primary and supplemental output currents of said bit circuits, and selectable means for actuating said supplemental transistor means.

Claim 22

A digital to analog converter comprising a plurality of bit circuits arranged in a resistance ladder of progressive binary order and functionally grouped into four-bit quads, each bit circuit including a primary transistor means adapted to draw a predetermined amount of output current when its associated bit circuit is actuated, a transistor bias circuit for said bit circuits, and means for selecting between binary and BCD operation modes, said means comprising: for each transistor means of each bit circuit in the higher than first order quads, an associated area-scaled supplemental transistor means internal to said DAC, each of said supplemental transistor means being actuable to draw a supplemental output current of sufficient magnitude to establish a BCD relationship between the total of the primary and supplemental output currents of said bit circuits, and selectable means for actuating said supplemental transistor means.

Claim 23

The DAC of claim 18, wherein said bias circuit comprises the combination of a bias line for the transistors of said bit circuits, BCD and binary NPN transistor means connected in circuit respectively with BCD and binary bias resistors to establish a bias voltage for said bias line as determined by the currents through said resistors, and means for applying bias current through said bias transistors and resistors, each supplemental transistor means comprises an NPN transistor means having its emitter connected in circuit with the emitter of one of said bias transistor means, and said selectable actuating means comprises means for selectably applying a cutoff voltage signal to the emitters of either said supplemental and said one bias transistor means, or to the emitter of the other bias transistor means.

Claim 24

The DAC of claim 19, said means for applying a cutoff voltage signal comprising the combination of a differential switch having a first branch connected to the emitters of said supplemental and said BCD bias transistor means, a second branch connected to the emitter of said binary bias transistor means, means for transmitting a switching signal to one of said branches, and a cutoff voltage source connected in circuit with said differential switch for transmission to said bias circuit.

Claim 25

The DAC of claim 20, said means for transmitting a switching signal comprising a zener diode connected in circuit with the first branch of said differential switch, and means for transmitting an over-voltage to cause permanent short circuiting of said diode.

Claim 26

The DAC of claim 19, and further including current source means connected in circuit with said supplemental transistor means for directing an additional current through said BCD bias resistor, the magnitude of said additional current being sufficient to increase the bias line voltage during BCD mode operation to a level at which the BCD full-scale output current is substantially equal to the binary full-scale output current.

Claim 27

The DAC of claim 18, each of said bit circuit transistor means comprising NPN transistors, and at least some of said supplemental transistor means comprising second emitters on the primary transistor for their respective bit circuits.

Claim 28

The DAC of claim 18, said resistance ladder being divided into a master ladder portion having a terminating means for generating a remainder signal, and a slave ladder portion dividing said remainder signal among the primary transistor means of the slave portion bit circuits, the number of bit circuits allocated to said master and slave portions each being an uneven multiple of four.

Claim 29

The DAC of claim 24, each of said supplemental transistor means being located in the slave ladder portion, and further including transistor switch means in the master ladder portion connected in circuit with said supplemental transistor means, and means for disabling said transistor switch means during binary mode operation so as to prevent supplemental current flow.

Claim 30

The DAC of claim 25, said bias circuit including first and second NPN transistor means connected respectively in circuit with first and second bias resistors to provide binary and BCD bias voltages, and selectable means for controlling the bias mode of said ladder by applying a cutoff voltage signal to the emitter of a desired one of said bias transistors, said transistor switch means comprising an NPN transistor means having an emitter connected in circuit with the emitter of said BCD bias transistor so that a cutoff signal applied to said BCD bias transistor also cuts off said switching transistor.

Claim 31

The DAC of claim 25, said transistor switch means comprising individual transistors connected in circuit respectively with each quad of supplemental transistor means, the emitters of said supplemental and switching transistors being area-scaled to increase the output current levels for the higher than first order quads to a BCD level.