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US5608204A
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Image cell for an image-recorder chip, for protection of high input signal dynamics onto reduced output signal dynamics
Assignee: INSTITUT fur MIKROELEKTRONIK STUTTGART
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Filing: 1993-03-23
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Granted: 1997-03-04
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Expires: 2013-03-23
Abstract
Abstract Disclosed is an image-recorder chip having a multiplicity of image cells provided with field-effect transistors disposed in the form of a two dimensional array and having a readout logic. This present invention is directed to the object of projection of high input signal dynamics onto reduced output signal dynamics, and is distinguished by the arrangement of the light-sensitive element of each image cell being connected between one electrode of a first MOS transistor and gate of a second MOS transistor, and by the other electrode of the first MOS transistor being connected to the one pole of a voltage supply source.
Inventors
- 👤 Bernd Hofflinger
- 👤 Marc Landgraf
- 👤 Ulrich Seger
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 11:37
CPC Classifications
H; H04; H04N; H04N25/00; H04N25/50; H04N25/57; H04N25/571; H04N25/573; H04N25/70; H04N25/76; H10; H10F; H10F39/00; H10F39/10; H10F39/12; H10F39/18; H10F39/80; H10F39/803; H10F39/805; H10F39/8057
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
212 words
An image cell having field-effect transistors, providing a light-sensitive element in particular, for an image-recorder chip comprising a multiplicity of such image cells disposed in form of a two-dimensional array and a readout logic, for transference of high input signal dynamics onto reduced output signal dynamics, wherein the light-sensitive element of the image cell (11 . . . 23) being connected between one electrode of a first MOS transistor (M1) and the gate Of a second MOS transistor (M2), a control voltage is applied to the gate of said first MOS transistor (M1) by which a compression of said input signal dynamics is controlled, another electrode of said first MOS transistor (M1) is connected to one polarity side (V ss ) of a voltage supply source, and an output signal being tapped at a second electrode of said second MOS transistor (2) by a control voltage by means of which the compression of said input signal dynamics can be controlled being applied to the gate of said first MOS transistor (M1), by the other electrode of said first MOS transistor (M1) being connected to the one pole (V ss ) of a voltage supply source, and by the output signal being tapped at the second electrode of said second MOS transistor (2).
Claim 2
Dependent Claim
212 words
An image cell having field-effect transistors, providing a light-sensitive element in particular, for an image-recorder chip comprising a multiplicity of such image cells disposed in form of a two-dimensional array and a readout logic, for transference of high input signal dynamics onto reduced output signal dynamics, wherein the light-sensitive element of the image cell (11 . . . 23) being connected between one electrode of a first MOS transistor (M1) and the gate Of a second MOS transistor (M2), a control voltage is applied to the gate of said first MOS transistor (M1) by which a compression of said input signal dynamics is controlled, another electrode of said first MOS transistor (M1) is connected to one polarity side (V ss ) of a voltage supply source, and an output signal being tapped at a second electrode of said second MOS transistor (2) by a control voltage by means of which the compression of said input signal dynamics can be controlled being applied to the gate of said first MOS transistor (M1), by the other electrode of said first MOS transistor (M1) being connected to the one pole (V ss ) of a voltage supply source, and by the output signal being tapped at the second electrode of said second MOS transistor (2).
Claim 3
Dependent Claim
28 words
An image cell according to claim 1, wherein one electrode of said first MOS transistor (M1) being the source electrode and the other electrode being the drain electrode.
Claim 4
Dependent Claim
23 words
An image cell according to claim 1 or 2, wherein said light-sensitive element being the one electrode of said first MOS transistor (M1).
Claim 5
Dependent Claim
39 words
An image cell according to claim 1, wherein a drain electrode and said gate of said first MOS transistor (M1) being short-circuited and applied to a fixed potential (V ss ) so that a logarithmic characteristic line is yielded.
Claim 6
Dependent Claim
28 words
An image cell according to claim 1, wherein said second MOS transistor (M2) being connected as a source follower and being a part of a first readout amplifier.
Claim 7
Dependent Claim
60 words
An image cell according to claim 5, further comprising a two-stage designed second readout amplifier (M3a, M4), being connected with said readout amplifier, wherein a first stage of said two-stage designed Second readout amplifier (M3a, M4) picks up little quiescent current during non-readout and a second stage (M4) is designed as a power stage which only becomes active for readout.
Claim 8
Dependent Claim
24 words
An image cell according to claim 5 or 6, further comprising a MOS transistor (M2a, M3) serving as a load for said source follower.
Claim 9
Dependent Claim
28 words
An image cell according to claim 1, further comprising a metal layer (A1) covering the regions which are not light-sensitive and being utilized as a power supply line.
Claim 10
Dependent Claim
36 words
An image-recorder chip having image cells according to claim 1, further comprising a readout logic (row -- sel, 31 . . . 33) permitting random access to the individual image cells (11 . . . 23).
Claim 11
Dependent Claim
168 words
An image cell comprising field-effect transistors, providing a light-sensitive element in particular, for an image-recorder chip comprising a multiplicity of such image cells disposed in form of a two-dimensional array and a readout logic, for the transformation of high input-signal dynamics to reduced output-signal dynamics, wherein the light-sensitive element of each image cell (11 . . . 23) is connected between one electrode of a first MOS transistor (M1) and a gate of a second MOS transistor (M2), a control voltage is applied to a gate of said first MOS transistor in order to control compression of said input signal dynamics, the other electrode of said first MOS transistor is connected to one polarity side (V ss , if M1 is a PMOS transistor) of a voltage supply source, and an output signal is tapped at one electrode of said second MOS transistor (M2), while its other electrode is connected to one polarity side (V ss , if M2 is a PMOS transistor) of a voltage supply source.
Claim 12
Dependent Claim
168 words
An image cell comprising field-effect transistors, providing a light-sensitive element in particular, for an image-recorder chip comprising a multiplicity of such image cells disposed in form of a two-dimensional array and a readout logic, for the transformation of high input-signal dynamics to reduced output-signal dynamics, wherein the light-sensitive element of each image cell (11 . . . 23) is connected between one electrode of a first MOS transistor (M1) and a gate of a second MOS transistor (M2), a control voltage is applied to a gate of said first MOS transistor in order to control compression of said input signal dynamics, the other electrode of said first MOS transistor is connected to one polarity side (V ss , if M1 is a PMOS transistor) of a voltage supply source, and an output signal is tapped at one electrode of said second MOS transistor (M2), while its other electrode is connected to one polarity side (V ss , if M2 is a PMOS transistor) of a voltage supply source.
References Cited (Backward Citations)
US5146074A
Cited
US5153420A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-03-03 | 2000-09-02 | 2001-03-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-03-03 | 2004-09-02 | 2005-03-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-03-03 | 2008-09-02 | 2009-03-04 | $7700.00 | Window Closed / Lapsed |