Integrated data processing system including CPU core and parallel, independently operating DSP module and having multiple operating modes

Claim 1

An integrated circuit structure having a central processing unit (CPU) formed as a part thereof, the integrated circuit structure comprising: an execution unit that executes instructions to perform data processing operations to process data items; a plurality of general purpose input/output pins, each of which can be connected to provide external signals and/or receive external signals from an external element; configuration circuitry connected to the CPU to configure the CPU for operation in an operating mode selected from a plurality of possible operating modes, the possible operating modes including (i) a first operating mode wherein the CPU is connected via an internal bus to an internal memory storage element formed as part of the integrated circuit structure and retrieves instructions and data items for use by the execution unit exclusively from the internal memory storage element, whereby all of the plurality of general purpose input/output pins remain available to provide and/or receive the external signals; (ii) a second operating mode wherein the CPU retrieves instructions and data items for use by the execution unit from an external memory storage element that is not formed as part of the integrated circuit structure and the external memory storage element being coupled to the execution unit via a first external bus that is connected to a first portion of the plurality of general purpose input/output pins, whereby a second portion of the plurality of general purpose input/output pins remains available to provide and/or receive the external signals; and (iii) a third operating mode wherein the central processing unit retrieves instructions and data items for use by the execution unit from at least one external storage element not formed as part of the integrated circuit structure, the at least one external storage element being coupled to the execution unit via a second external bus that is connected to a third portion of the plurality of general purpose input/output pins such that the external signals can be provided and/or received by the integrated circuit structure only if external input/output circuitry is connected to the second external bus.