US4594651A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Concurrent processor for control
Assignee: General Electric Co
•
Filing: 1984-01-18
•
Granted: 1986-06-10
•
Expires: 2004-01-18
Abstract
Abstract This computer architecture is optimized for computing the state transitions of a controller, whereas conventional computers are optimized for data manipulation. The concurrent processor for control efficiently implements both the continuous and discrete control functions and has a processing element with two parts, the continuous and discrete processing elements. An arbitrary number of processing elements in a linear array have nearest-neighbor communications, and a general purpose microprocessor is provided to interact with them. Continuous states are computed concurrently and there is provision for interaction between continuous and discrete controls.
Inventors
- 👤 Vijay C. Jaswa
- 👤 Charles E. Thomas
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 20:29
CPC Classifications
G; G05; G05B; G05B19/00; G05B19/02; G05B19/18; G05B19/414; G05B19/4148; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/30003; G06F9/30007; G06F9/3001; G06F9/30021; G06F9/30029; G06F9/30145; G05B2219/00; G05B2219/30; G05B2219/34; G05B2219/34403
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
88 words
A digital controller comprising: multiple substantially identical processing elements interconnected in a linear array; each processing element having a continuous and a discrete processing element in two-way communication, the first computing continuous state variables from at least one row of a matrix equation, and the second simultaneously and asynchronously computing discrete state variables; and communication means to transfer present continuous state variables in sequence to said processing elements which concurrently calculate next continuous state variables; said processing elements including means for outputting computed state variables to controlled equipment.
Claim 2
Dependent Claim
88 words
A digital controller comprising: multiple substantially identical processing elements interconnected in a linear array; each processing element having a continuous and a discrete processing element in two-way communication, the first computing continuous state variables from at least one row of a matrix equation, and the second simultaneously and asynchronously computing discrete state variables; and communication means to transfer present continuous state variables in sequence to said processing elements which concurrently calculate next continuous state variables; said processing elements including means for outputting computed state variables to controlled equipment.
Claim 3
Dependent Claim
17 words
The digital controller of claim 1 further including a general purpose microprocessor interacting with said processing elements.
Claim 4
Dependent Claim
38 words
The digital controller of claim 2 wherein selected continuous processing elements have external inputs from the controlled equipment, and said communication means transfers said external inputs to processing elements as needed to calculate said next continuous state variables.
Claim 5
Dependent Claim
23 words
The digital controller of claim 2 wherein said continuous processing elements are hard-wired controllers and said discrete processing elements are program driven controllers.
Claim 6
Dependent Claim
55 words
The digital controller of claim 1 wherein every continuous processing element is comprised of memory means to store matrix equation coefficients and present continuous state variables including those transferred from other processing elements, input-output means, multiplier-accumulator means for multiplying said coefficients and present continuous state variables and summing the products, and first data bus means.
Claim 7
Dependent Claim
60 words
The digital controller of claim 5 wherein every discrete processing element is comprised of program memory means, input-output memory means, logic means to compute Boolean equations and said discrete state variables, arithmetic means to compare said present continuous state variables with a threshold, second data bus means, and means for joining said first and second data bus means upon command.
Claim 8
Dependent Claim
127 words
A concurrent processor for control comprising: multiple substantially identical processing elements that are interconnected in a linear array; each processing element having a continuous and a discrete processing element which operate simultaneously and are in two-way communication, the first computing continuous state variables and one or more rows of a state equation in discretized matrix form, and the second computing discrete state variables; at least some of said processing elements having ports for external inputs from controlled equipment and to outut computed state variables; serial communication links between neighboring processing elements to establish loops to transfer present continuous state values and external inputs which are needed to calculate next continuous state values concurrently in all processing elements; and a general purpose microprocessor interacting with every processing element.
Claim 9
Dependent Claim
127 words
A concurrent processor for control comprising: multiple substantially identical processing elements that are interconnected in a linear array; each processing element having a continuous and a discrete processing element which operate simultaneously and are in two-way communication, the first computing continuous state variables and one or more rows of a state equation in discretized matrix form, and the second computing discrete state variables; at least some of said processing elements having ports for external inputs from controlled equipment and to outut computed state variables; serial communication links between neighboring processing elements to establish loops to transfer present continuous state values and external inputs which are needed to calculate next continuous state values concurrently in all processing elements; and a general purpose microprocessor interacting with every processing element.
Claim 10
Dependent Claim
60 words
The concurrent processor of claim 7 wherein every continuous processing element is comprised of memory means for storing state equation coefficients and present continuous state values and external inputs including those transferred from other processing elements, input-output means, and multiplier-accumulator means for multiplying coefficients by said present continuous state values and external inputs and deriving the sum of the products.
Claim 11
Dependent Claim
23 words
The concurrent processor of claim 8 wherein said continuous processing elements are hard-wired controls and said discrete processing elements are program driven controls.
Claim 12
Dependent Claim
53 words
The concurrent processor of claim 8 wherein said memory means, input-output means, and multiplier-accumulator means have access to a first data bus, and each discrete processing element has a second data bus, and means for joining said first and second data buses upon command from bus arbitration logic in each discrete processing element.
Claim 13
Dependent Claim
59 words
The concurrent processor of claim 10 wherein every discrete processing element is further comprised of program memory means, input-output memory means, a logic unit to compute Boolean equations, and an arithmetic unit to compare said present continuous state variables with a threshold, said last-mentioned units and said program and input-output memory means having access to said second data bus.
Claim 14
Dependent Claim
41 words
The digital controller of claim 7 wherein said discrete processing elements are program driven controllers and have a specialized instruction set with conditional execution capability to allow a discrete state variable to affect a continuous state variable in a single instruction.
Claim 15
Dependent Claim
125 words
A digital controller processing element comprising: a continuous and a discrete processing element which operate independently and simultaneously and have respective data bus means that are joined upon command from the latter processing element; said continuous processing element computing next continuous state variables and one or more rows of a state equation in discretized matrix form, and comprised of input/output means, memory means to at least store matrix equation coefficients and present continuous state variables, and means for multiplying said coefficients and present continuous state variables and summing the products; said discrete processing element being comprised of program memory means, input/output memory means, logic means to comput Boolean functions and discrete state variables, and arithmetic means to compare said continuous state variables with a threshold.
Claim 16
Dependent Claim
125 words
A digital controller processing element comprising: a continuous and a discrete processing element which operate independently and simultaneously and have respective data bus means that are joined upon command from the latter processing element; said continuous processing element computing next continuous state variables and one or more rows of a state equation in discretized matrix form, and comprised of input/output means, memory means to at least store matrix equation coefficients and present continuous state variables, and means for multiplying said coefficients and present continuous state variables and summing the products; said discrete processing element being comprised of program memory means, input/output memory means, logic means to comput Boolean functions and discrete state variables, and arithmetic means to compare said continuous state variables with a threshold.
Claim 17
Dependent Claim
28 words
The processing element of claim 13 wherein at least one of said continuous and discrete processing elements have external inputs which are utilized to calculate said state variables.
Claim 18
Dependent Claim
47 words
The processing element of claim 13 wherein said discrete processing element has a simplified instruction set and a field in the instruction determines a condition to be satisfied for instruction execution, to allow a discrete state variable to affect a continuous state variable in a single instruction.
Claim 19
Dependent Claim
31 words
The processing element of claim 15 wherein said input/output memory means has a cache to store the most recently used bits to avoid repeated fetches of the same discrete state variables.
References Cited (Backward Citations)
US3248706A
Cited
US4022555A
Cited
US4425664A
Cited
US4118771A
Cited
US4152761A
Cited
US4128876A
Cited
US4193022A
Cited
US4395758A
Cited
US4443846A
Cited
US4462072A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-06-09 | 1989-12-09 | 1990-06-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-06-09 | 1993-12-09 | 1994-06-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-06-09 | 1997-12-09 | 1998-06-10 | $7700.00 | Window Closed / Lapsed |