Method and apparatus for storage and retrieval of a texture map in a graphics display system

Claim 2

In a computer controlled display system, a method for storing and accessing a plurality of modified MIP mapped texture maps, said method comprising the steps of: a) storing corresponding pages of a first texture map and a second texture map so that said corresponding pages of said first and said second texture map are stored contiguously; b) storing even pixels of said first and second texture maps in a first memory bank; c) storing odd pixels of said first and second texture maps in a second memory bank; d) providing a pixel address, said pixel address including an X part and a Y part; e) adding a one value to said Y part to create a Y+1 part; f) determining if said pixel address is an odd address or an even address; g) providing said X part to said first memory bank and said second memory bank; h) if said pixel address is an odd address, providing said Y+1 pan to said first memory bank and said Y part to said second memory bank; and i) if said pixel address is an even address, providing said Y part to said first memory bank and said Y+1 pan to said second memory bank.

Claim 3

The method as recited in claim 7 wherein said first and second texture maps have a resolution of N x N and said step of providing said pixel address is further comprised of the steps of: a) receiving a first coordinate and a second coordinate for a pixel in a texture map; b) shifting said first coordinate by n bits to generate said X part, wherein n is equal to log 2 N; c. using said second coordinate as said Y part: and d) combining said X part with said Y part to form said pixel address.

Claim 4

The method as recited in claim 2 wherein said step of combining said X part with said Y part is further comprised of the step performing a logical OR operation between said X part and said Y part to form said pixel address.

Claim 5

The method as recited in claim 3 further comprising the steps of: a) providing an offset value, said offset value corresponding to a predetermined texture map and a predetermined page; b) performing a logical OR operation between said pixel address and said offset value to form an offset pixel address; and c) providing said offset pixel address as said pixel address.

Claim 6

The method of claim 4 wherein said offset value is formed by summing the product of a total number of said corresponding pages and a page size for each of said corresponding pages for each said texture map preceding said predetermined page, and a number of said corresponding pages and said page size for each of said corresponding pages for each said texture map preceding said predetermined texture map within said predetermined page.

Claim 7

The method of claim 4 wherein said offset value is formed by summing an M value and a T value, said T value being obtained from a map identifier for said predetermined texture map and a highest resolution page, and said M value being obtained from a page identifier of said predetermined page and said highest resolution page.

Claim 8

The method of claim 6 wherein said T value is equal to said map identifier shifted by a first value, said first value being a product of two and a difference of n and said page identifier.

Claim 9

The method of claim 6 wherein said M value is equal to a sum of all of the products of a number of said texture maps and the size of said corresponding pages of each of said texture maps.

Claim 10

The method of claim 8 wherein said M value is determined by performing a lookup in a lookup table using said page identifier and said highest resolution page.

Claim 11

The method of claim 6 wherein said M value is determined by performing a lookup in a lookup table using said page identifier and said highest resolution page.

Claim 12

A rendering component in combination with a storage means, said storage means for storing a plurality of texture maps, said plurality of texture maps including a first texture map and a second texture map, said rendering component comprised of: a first set of address conductors for providing the high order bits of a first and a second pixel address in said storage means; a second set of address conductors for providing the low order bits of said first pixel address in said storage means; a third set of address conductors for providing the low order bits of said second pixel address in said storage means; and said storage means for storing said texture maps in modified MIP map form so that corresponding pages of said first and second texture maps are stored contiguously, said storage means further comprising: a first memory bank for storing even pixels of said first and second texture maps, said first memory bank coupled to receive addresses from said first and second sets of address conductors; a second memory bank for storing odd pixels of said first and second texture maps, said second memory bank coupled to receive addresses from said first and third sets of address conductors.

Claim 13

A rendering component in combination with a storage means, said storage means for storing a plurality of texture maps, said plurality of texture maps including a first texture map and a second texture map, said rendering component comprised of: a first set of address conductors for providing the high order bits of a first and a second pixel address in said storage means; a second set of address conductors for providing the low order bits of said first pixel address in said storage means; a third set of address conductors for providing the low order bits of said second pixel address in said storage means; and said storage means for storing said texture maps in modified MIP map form so that corresponding pages of said first and second texture maps are stored contiguously, said storage means further comprising: a first memory bank for storing even pixels of said first and second texture maps, said first memory bank coupled to receive addresses from said first and second sets of address conductors; a second memory bank for storing odd pixels of said first and second texture maps, said second memory bank coupled to receive addresses from said first and third sets of address conductors.

Claim 14

The combination as recited in claim 11 wherein said rendering component is further comprised of means for causing said first pixel address to be an even address.

Claim 15

The combination as recited in claim 12 wherein said means for causing said first pixel address to be an even address is further comprised of: means for determining if said first pixel address is an odd address; and means for swapping said first pixel address with said second pixel address if said first pixel address is an odd address.

Claim 16

A computer system having a texture map circuit, said texture map circuit comprising: a memory operative to store a plurality of texture maps, said memory having an N bit address input, each texture map of said plurality of texture maps being in modified MIP map form, said memory operative to store corresponding pages between said plurality of texture maps at contiguous memory addresses; an address circuit having a pixel address input and an address output, wherein said address output is coupled to said address input, said address output operative to output L addresses responsive to receiving a pixel identifier for said address input and said pixel address input.

Claim 17

A computer system having a texture map circuit, said texture map circuit comprising: a memory operative to store a plurality of texture maps, said memory having an N bit address input, each texture map of said plurality of texture maps being in modified MIP map form, said memory operative to store corresponding pages between said plurality of texture maps at contiguous memory addresses; an address circuit having a pixel address input and an address output, wherein said address output is coupled to said address input, said address output operative to output L addresses responsive to receiving a pixel identifier for said address input and said pixel address input.

Claim 18

The computer system of claim 14 wherein said pixel identifier includes a texture map indicator, a page indicator, an x value and a y value, said address circuit further comprises: a shift circuit coupled to receive said x value and an n value, where said n value corresponds to a size of a row of pixels in a texture map corresponding to said texture map indicator, said shift circuit having a shifted x output, said shifted x corresponding to said x value being shifted by said n value; a combining circuit coupled to receive said y value and said shifted x, said combining circuit having a non-offset address output, said non-offset address corresponding to said y value being combined with said shifted x; an offset generation circuit coupled to receive said texture map indicator and said page indicator, said offset generation circuit having an offset output, said offset corresponding to said texture map indicator and said page indicator; and a second combining circuit coupled to receive said non-offset address and said offset, said second combining circuit having an address output, said address output for outputting one address of said L addresses, said one address corresponding to said non-offset address being combined with said offset.

Claim 19

The computer system of claim 15 wherein said shift circuit includes a shift register.

Claim 20

The computer system of claim 15 wherein said combining circuit includes a first plurality of logical OR circuits, and said second combining circuit includes a second plurality of logical OR circuits.

Claim 21

The computer system of claim 15 wherein n equals the log base two of said size.

Claim 22

The computer system of claim 15 wherein said page indicator includes a real number and wherein said page indicator corresponds to a first page having a next greater resolution than said page indicator and said page indicator corresponds to a second page having a next less than or equal to resolution than said page indicator.

Claim 23

A circuit having a texture map pixel output and a pixel address input, said circuit comprising: a memory, said memory operative to store a first texture map and a second texture map, said first texture map including a first N×N page and a first N/M×N/M page, said second texture map including a second N×N page and a second N/M×N/M page, said first N×N page and said second N×N page being stored contiguously, said first N/M×N/M page and said second N/M×N/M page being stored contiguously, said memory having a pixel output; and a circuit having an address output, said address output being coupled to said memory, said address output operative to communicate a plurality of addresses to said memory in response to receiving said pixel address.

Claim 24

A circuit having a texture map pixel output and a pixel address input, said circuit comprising: a memory, said memory operative to store a first texture map and a second texture map, said first texture map including a first N×N page and a first N/M×N/M page, said second texture map including a second N×N page and a second N/M×N/M page, said first N×N page and said second N×N page being stored contiguously, said first N/M×N/M page and said second N/M×N/M page being stored contiguously, said memory having a pixel output; and a circuit having an address output, said address output being coupled to said memory, said address output operative to communicate a plurality of addresses to said memory in response to receiving said pixel address.

Claim 25

The circuit of claim 20 wherein N and M are integers greater than 1 and wherein M is less than N.

Claim 28

The method of claim 22 wherein said step of storing each of said groups of said corresponding pages of each of said plurality of said texture maps includes storing a first group of said corresponding pages of said texture maps which includes a highest resolution of said corresponding pages of said plurality of said texture :maps and storing a last group of said corresponding pages of each of said plurality of said texture maps which includes a lowest resolution of said corresponding pages of said texture maps.

Claim 29

The method of claim 22 wherein said step of using said texture map store to perform texture mapping of images includes the step of accessing a desired pixel of a desired page of a desired texture map by: a) receiving a pixel identifier, a page identifier, and a texture map identifier; b) determining a texture map location by shifting said texture map identifier a first number of bits, wherein said first number of bits includes the number of bits which comprise said pixel identifier; c) determining a page location by summing a size of each of said groups of pages preceding a group of pages of said texture maps which includes said desired page; d) summing said page location with said texture map location to generate an offset; e) performing a bitwise logical or operation between said offset and said pixel identifier to generate an address; and f) accessing said desired pixel of said desired page of said desired texture map at said address in said texture map store.

Claim 30

The method of claim 24 wherein said step of receiving said pixel identifier includes: a) receiving an x coordinate and a y coordinate; b) shifting said x coordinate by a second number of bits to generate a shifted x coordinate, said second number of bits being a number of bits which comprise said y coordinate; and c) performing a bitwise logical OR between said shifted x coordinate and said y coordinate to generate said pixel identifier.