FFT-based channelizer and combiner employing residue-adder-implemented phase advance

Claim 1

A wideband cellular-telephone-receiver circuit for receiving a composite signal comprising a plurality of different-frequency carriers modulated by respective modulation signals and for extracting a plurality of channel output signals representing respective ones of the modulation signals, the receiver circuit comprising: A) a digitizing circuit for processing the composite signal to produce digital-sequence signals representing a digital input sample sequence; B) a discrete-Fourier-transform circuit for performing a sequence of overall Fourier-transform operations, each overall Fourier-transform operation comprising constituent Fourier-transform computations executed in successive passes through respective passes' computation values to compute as computation values of the last pass the discrete Fourier transform of a K-element transform input record consisting of computation values of the first pass, where K=JK' and J, K, and K' are positive integers, and for generating a plurality of channel output signals, each of which represents corresponding elements of discrete Fourier transforms computed in successive overall Fourier-transform operations; C) a coefficient-multiplication circuit for receiving successive input-sequence segments of the input sample sequence, each input-sequence segment being offset from the previous segment by M samples, where M is a non-zero integer, for multiplying the elements of each input-sequence segment by corresponding coefficients of a base finite-impulse-response filter and so time-aliasing the products as to produce the computation values of the first pass, and for generating multiplication-circuit output signals representing those transform-input-record elements, whereby each channel signal is indicative of the response, to the input-sequence segment, of a respective finite-impulse-response filter whose frequency response is that of the base finite-impulse-response filter translated by a respective different frequency offset; D) memory circuitry, comprising addressable memory locations, for receiving memory address signals representing addresses for respective computation values, receiving the computation values, and, between uses thereof, storing the computation values in and fetching the computation values from memory locations designated by the memory-address signals; and E) address-generation circuitry, including address-computation circuitry for determining the memory addresses to be used for storing and fetching respective computation values for each pass, for generating and applying to the memory circuitry memory-address signals representing those memory addresses, the circuitry for generating the addresses for storing or fetching one pass's computation values comprising: i) a base-address generator for generating, for each computation value, base-address signals representing a base address that is the same in successive overall Fourier-transform operations for corresponding elements of corresponding passes; ii) a modulo-K' adder, responsive to the base-address signals and adapted to receive offset-address signals, for computing, as the relative memory address for each of the computation values of that pass in a given overall Fourier-transform operation, the sum, modulo K', of the base address for that computation value and the offset address for that overall Fourier-transform operation; and iii) an offset-address generator for generating and applying to the modulo-K' adder, for each overall Fourier-transform operation, an offset-address signal representing a quantity that so progresses between successive overall Fourier-transform operations that each channel signal represents the output of its respective finite-impulse-response filter translated to a common frequency band.