Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
223 words
A system for recombining a message transmitted by a frequency hopping transmitter operating in accordance with a predetermined frequency hopping program, including a predetermined dwell time, which is unknown at a receiving end of the system, comprising: a digital FFT search receiver including a wire band receiving circuit for receiving an analog input signal and operating to convert the frequency band of the transmitter to an IF position, an analog-to-digital converter connected to said receiving circuit for converting the analog input signal into a digital signal, and a FFT processor connected to said analog-to-digital converter for determining, within a predetermined time window, the instantaneous frequency occupancy of the frequency band by determining at what frequency a complete data record is output by said analog-to-digital converter during a predetermined system cycle time which is the time between the generation of two complete successive records and which is shorter than the predetermined dwell time of the frequency hopping transmitter; at least one interception frequency receiver connected to said FFT processor and operated thereby to switch the respective instantaneous transmitting frequency; a digital storage means connected to said analog-to-digital converter for temporarily storing and delaying the digital signal; and a digital-to-analog converter connected between said digital storage means and said at least one instantaneous receiver for converting the stored digital signal into the original analog signal.
Claim 2
Independent Claim
223 words
A system for recombining a message transmitted by a frequency hopping transmitter operating in accordance with a predetermined frequency hopping program, including a predetermined dwell time, which is unknown at a receiving end of the system, comprising: a digital FFT search receiver including a wire band receiving circuit for receiving an analog input signal and operating to convert the frequency band of the transmitter to an IF position, an analog-to-digital converter connected to said receiving circuit for converting the analog input signal into a digital signal, and a FFT processor connected to said analog-to-digital converter for determining, within a predetermined time window, the instantaneous frequency occupancy of the frequency band by determining at what frequency a complete data record is output by said analog-to-digital converter during a predetermined system cycle time which is the time between the generation of two complete successive records and which is shorter than the predetermined dwell time of the frequency hopping transmitter; at least one interception frequency receiver connected to said FFT processor and operated thereby to switch the respective instantaneous transmitting frequency; a digital storage means connected to said analog-to-digital converter for temporarily storing and delaying the digital signal; and a digital-to-analog converter connected between said digital storage means and said at least one instantaneous receiver for converting the stored digital signal into the original analog signal.
Claim 3
Dependent Claim
37 words
The system of claim 1, wherein: said digital storage means comprising means for providing a delay time equal to the dead time of the FFT receiver including the setting time of said at least one instantaneous receiver.
Claim 4
Dependent Claim
43 words
The system of claim 1, wherein: said digital storage means comprises means for providing a delay time equal to the dead time of the FFT receiver, including the setting time of said at least one instantaneous receiver, plus the predetermined system cycle time.
Claim 5
Dependent Claim
140 words
The system of claim 3, and further comprising: first and second frequency storage means connected to said FFT processor for alternately storing transmitting frequencies of the frequency hopping transmitter; a receiving signal detector connected to said interception receiver; a switch connected between said interception receiver and said first and second frequency storage means; and a logic circuit connected between said receiving signal detector and said switch and operating to switch said interception receiver from said one frequency storage means to the other frequency storage means at the start of a new system cycle when the receiver frequency is present during the entire system cycle, and to switch the interception receiver to the frequency storage means having the last-stored frequency and suppressing frequency switching at the start of the next system cycle when the received frequency disappears during a system cycle.