Semiconductor integrated circuit device and a manufacturing method thereof

Claim 1

A semiconductor integrated circuit device including: a first bit line to which a plurality of memory cells are connected, each memory cell having a memory cell selection MISFET and a capacitor connected in series therewith; a second bit line connected to a sense amplifier and extending parallel to the first bit line; and a switching MISFET connected between the second bit line and the first bit line to connect the first bit line to the second bit line, said semiconductor integrated circuit device comprising: a semiconductor substrate having on the main surface thereof a memory cell region and a switch region adjacent to the memory cell region; a plurality of first active regions arranged in row and column directions in the memory cell region; a plurality of second active regions arranged in row and column directions in the switch region; in the memory cell region, a plurality of word lines extending in a row direction and arranged with a first pitch in a column direction, a pair of adjoining word lines being arranged to cross the first active regions; in the switch region, a plurality of interconnections extending in a row direction and arranged with the first pitch in a column direction, a pair of adjoining interconnections being arranged to cross the second active regions; in the memory cell region, a first semiconductor region located inside the pair of adjoining word lines and in each of the first active regions, the first semiconductor region being connected to a sub-bit line; in the memory cell region, a second semiconductor region located outside the pair of adjoining word lines and in each of the first active regions, the second semiconductor region being connected to the capacitor; in the switch region, a third semiconductor region located inside the pair of adjoining interconnections and in each of the second active regions, the third semiconductor region being connected to the sub-bit line; in the switch region, a fourth semiconductor region located outside the pair of adjoining interconnections and in each of the second active regions; and in the memory cell and the switch region, a plurality of main bit lines extending in a column direction and arranged with a specified pitch in a row direction, each of the main bit lines being connected to the fourth semiconductor region in the switch region; wherein the memory cell selection MISFET comprises each of the word lines and the first and second semiconductor regions, and the switching MISFET comprises each of the interconnections and the third and fourth semiconductor regions, and wherein the shape of each of said first active regions is substantially the same as the shape of each of the second active regions.