Method to fabricate a semiconductor memory device having an E-shaped storage node

Claim 1

A method for fabricating a dynamic random access memory (DRAM) having a capacitor comprising: forming field oxide regions in and on a semiconductor substrate; forming a gate silicon oxide layer over the surface of said semiconductor substrate; depositing a gate polysilicon layer overlying said gate silicon oxide layer and patterning said gate polysilicon to form gate electrodes; forming lightly doped drain regions within said semiconductor substrate; depositing and etching a spacer silicon oxide to form spacers on the sidewalls of said gate electrodes; forming source and drain regions within said semiconductor substrate; depositing a dielectric layer overlying said gate electrodes and the surfaces of said semiconductor substrate; depositing an insulating layer overlying said dielectric layer and planarizing said insulating layer; opening a contact through said insulating layer and said dielectric layer to one of said source and drain regions within said semiconductor substrate which will form a node of said capacitor; depositing a first layer of polysilicon overlying said insulating layer and filling said contact opening wherein a portion of said first polysilicon layer contacting one of said source and drain regions which forms said node will be the bottom electrode of said capacitor; etching away a portion of said first polysilicon layer wherein a well opening is formed above said contact opening; depositing a layer of silicon oxide overlying said first polysilicon layer and conformally within said well opening; etching back said silicon oxide layer to leave spacers on the sidewalls of said well opening; depositing a second layer of polysilicon overlying said first polysilicon layer and within said well opening; removing said second polysilicon layer except where said second polysilicon layer forms a plug within said well opening; removing said spacers on the walls of said well opening wherein gaps are left on either side of said plug; patterning said first polysilicon layer so that an E-shaped structure having three prongs is formed wherein the prongs of said E-shaped structure point upward and wherein said plug forms the central prong and wherein the outer two prongs are formed by said patterned first polysilicon layer and wherein said E-shaped structure forms the storage node of said capacitor; depositing a capacitor dielectric layer over all surfaces of said substrate wherein said capacitor dielectric layer covers the surfaces of said E-shaped structure; and depositing a third polysilicon layer overlying said capacitor dielectric layer wherein said third polysilicon layer covers and fills gaps of said E-shaped structure and wherein said third polysilicon layer forms the top electrode of said capacitor to complete formation of said DRAM with capacitor.

Claim 2

A method for fabricating a dynamic random access memory (DRAM) having a capacitor comprising: forming field oxide regions in and on a semiconductor substrate; forming a gate silicon oxide layer over the surface of said semiconductor substrate; depositing a gate polysilicon layer overlying said gate silicon oxide layer and patterning said gate polysilicon to form gate electrodes; forming lightly doped drain regions within said semiconductor substrate; depositing and etching a spacer silicon oxide to form spacers on the sidewalls of said gate electrodes; forming source and drain regions within said semiconductor substrate; depositing a dielectric layer overlying said gate electrodes and the surfaces of said semiconductor substrate; depositing an insulating layer overlying said dielectric layer and planarizing said insulating layer; opening a contact through said insulating layer and said dielectric layer to one of said source and drain regions within said semiconductor substrate which will form a node of said capacitor; depositing a first layer of polysilicon overlying said insulating layer and filling said contact opening wherein a portion of said first polysilicon layer contacting one of said source and drain regions which forms said node will be the bottom electrode of said capacitor; etching away a portion of said first polysilicon layer wherein a well opening is formed above said contact opening; depositing a layer of silicon oxide overlying said first polysilicon layer and conformally within said well opening; etching back said silicon oxide layer to leave spacers on the sidewalls of said well opening; depositing a second layer of polysilicon overlying said first polysilicon layer and within said well opening; removing said second polysilicon layer except where said second polysilicon layer forms a plug within said well opening; removing said spacers on the walls of said well opening wherein gaps are left on either side of said plug; patterning said first polysilicon layer so that an E-shaped structure having three prongs is formed wherein the prongs of said E-shaped structure point upward and wherein said plug forms the central prong and wherein the outer two prongs are formed by said patterned first polysilicon layer and wherein said E-shaped structure forms the storage node of said capacitor; depositing a capacitor dielectric layer over all surfaces of said substrate wherein said capacitor dielectric layer covers the surfaces of said E-shaped structure; and depositing a third polysilicon layer overlying said capacitor dielectric layer wherein said third polysilicon layer covers and fills gaps of said E-shaped structure and wherein said third polysilicon layer forms the top electrode of said capacitor to complete formation of said DRAM with capacitor.

Claim 20

A method for fabricating a dynamic random access memory (DRAM) having a capacitor comprising: selectively forming field oxide areas on the surface of a semiconductor substrate while leaving device areas for fabrication of semiconductor devices; forming device structures within said device areas of said semiconductor substrate wherein said device structures include a capacitor node contact region within said semiconductor substrate; and forming said capacitors by: depositing a dielectric layer overlying said semiconductor device structures; depositing an insulating layer overlying said dielectric layer and planarizing said insulating layer; opening a contact through said insulating layer and said dielectric layer to said capacitor node contact region; depositing a first layer of polysilicon overlying said insulating layer and filling said contact opening; etching away a portion of said first polysilicon layer wherein a well opening is formed above said contact opening; depositing a layer of silicon oxide overlying said first polysilicon layer and conformally within said well opening; etching back said silicon oxide layer to leave spacers on the sidewalls of said well opening; depositing a second layer of polysilicon overlying said first polysilicon layer and within said well opening; removing said second polysilicon layer except where said second polysilicon layer forms a plug within said well opening; removing said spacers on the walls of said well opening wherein gaps are left on either side of said plug; patterning said first polysilicon layer so that an E-shaped structure having three prongs is formed wherein the prongs of said E-shaped structure point upward and wherein said plug forms the central prong and wherein the outer two prongs are formed by said patterned first polysilicon layer; depositing a capacitor dielectric layer over all surfaces of said substrate wherein said capacitor dielectric layer covers the surfaces of said E-shaped structure; and depositing a third polysilicon layer overlying said capacitor dielectric layer wherein said third polysilicon layer covers and fills the gaps of said E-shaped structure to complete formation of said DRAM with capacitor.

Claim 21

A method for fabricating a dynamic random access memory (DRAM) having a capacitor comprising: selectively forming field oxide areas on the surface of a semiconductor substrate while leaving device areas for fabrication of semiconductor devices; forming device structures within said device areas of said semiconductor substrate wherein said device structures include a capacitor node contact region within said semiconductor substrate; and forming said capacitors by: depositing a dielectric layer overlying said semiconductor device structures; depositing an insulating layer overlying said dielectric layer and planarizing said insulating layer; opening a contact through said insulating layer and said dielectric layer to said capacitor node contact region; depositing a first layer of polysilicon overlying said insulating layer and filling said contact opening; etching away a portion of said first polysilicon layer wherein a well opening is formed above said contact opening; depositing a layer of silicon oxide overlying said first polysilicon layer and conformally within said well opening; etching back said silicon oxide layer to leave spacers on the sidewalls of said well opening; depositing a second layer of polysilicon overlying said first polysilicon layer and within said well opening; removing said second polysilicon layer except where said second polysilicon layer forms a plug within said well opening; removing said spacers on the walls of said well opening wherein gaps are left on either side of said plug; patterning said first polysilicon layer so that an E-shaped structure having three prongs is formed wherein the prongs of said E-shaped structure point upward and wherein said plug forms the central prong and wherein the outer two prongs are formed by said patterned first polysilicon layer; depositing a capacitor dielectric layer over all surfaces of said substrate wherein said capacitor dielectric layer covers the surfaces of said E-shaped structure; and depositing a third polysilicon layer overlying said capacitor dielectric layer wherein said third polysilicon layer covers and fills the gaps of said E-shaped structure to complete formation of said DRAM with capacitor.