Low thrash cache with selectable tile geometry

Claim 2

A cache memory for storing data from a source where each item of data is identified by an address having a plurality of bits, said memory comprising: means for receiving the address and having a plurality of bit conductors divided into at least a first group and a second group; a tag memory having an address port, and a data input and output means; a random access memory for storing the data, and having an address port; a multiplexer, coupled to said means for receiving the address, for selectively connecting one of the first and second groups of bit conductors to the address input ports of said tag memory and said random access memory and selectively connecting the other one of the first and second groups of bit conductors to the data input and output means of said tag memory in response to a control signal; means for comparing a first set of bits carried by the other one of the first and second groups of bit conductors to a second set of bits read from said tag memory, and producing a signal indicative of results of that comparison; and a controller which receives the signal from said means for comparing and responds thereto by reading data from said random access memory when the signal indicates a match the first and second sets of bits, or by reading data from the source when the signal indicates that the first and second sets of bits do not match.

Claim 3

The system as recited in claim 1 wherein said controller causes the data from the source to be stored into said random access memory and causes bits carried by the other group of bit conductors to be stored into said tag memory, when the signal indicates that the first and second sets of bits do not match.

Claim 4

In an image processing system having a frame buffer that stores an image formed of a plurality of pixels in which each pixel is identified by an address having a plurality of bits, and having a pixel utilization circuit; the improvement being a cache memory for controlling the transmission of pixels from the frame buffer to the utilization circuit and comprising: means for supplying a configuration control signal; a tag memory having an address port, and a data input and output means; a random access memory for storing pixels, and having an address port and a data input and output means; means for generating addresses of pixels to be processed by the utilization circuit and applying each address to a plurality of bit conductors divided into four groups; a multiplexer, coupled to said means for generating addresses, for selectively connecting two of the groups of bit conductors to the address ports of said tag memory and said random access memory and selectively connecting the other two groups of bit conductors to the data input and output means of said tag memory, the selective connecting being in response to said means for supplying a configuration control signal; means for comparing a first set of bits carried by the other two bit conductor groups to a second set of bits read from said tag memory, and producing a signal indicative of results of that comparison; and a controller which receives the signal from said means for comparing by reading a pixel from said random access memory when the signal indicates a match between the first and second sets of bits, or by reading a pixel from the frame buffer when the signal indicates that the first and second sets of bits do not match.

Claim 5

In an image processing system having a frame buffer that stores an image formed of a plurality of pixels in which each pixel is identified by an address having a plurality of bits, and having a pixel utilization circuit; the improvement being a cache memory for controlling the transmission of pixels from the frame buffer to the utilization circuit and comprising: means for supplying a configuration control signal; a tag memory having an address port, and a data input and output means; a random access memory for storing pixels, and having an address port and a data input and output means; means for generating addresses of pixels to be processed by the utilization circuit and applying each address to a plurality of bit conductors divided into four groups; a multiplexer, coupled to said means for generating addresses, for selectively connecting two of the groups of bit conductors to the address ports of said tag memory and said random access memory and selectively connecting the other two groups of bit conductors to the data input and output means of said tag memory, the selective connecting being in response to said means for supplying a configuration control signal; means for comparing a first set of bits carried by the other two bit conductor groups to a second set of bits read from said tag memory, and producing a signal indicative of results of that comparison; and a controller which receives the signal from said means for comparing by reading a pixel from said random access memory when the signal indicates a match between the first and second sets of bits, or by reading a pixel from the frame buffer when the signal indicates that the first and second sets of bits do not match.

Claim 6

The system as recited in claim 3 wherein said controller also stores the pixel from the frame buffer into said random access memory and stores bits carried by the other two group of bit conductors in said tag memory, when the signal indicates that the first and second sets of bits do not match.

Claim 7

The system as recited in claim 3 further including a set of staging latches which couple said multiplexer to the address port of said random access memory.

Claim 8

The system as recited in claim 3 wherein said further including a set of staging latches responsive to said controller for coupling said means for generating addresses of pixels to the frame buffer when the signal indicates that the first and second sets of bits do not match.