Graphics frame buffer with programmable tile size

Claim 1

A frame buffer storing pixel values in frame buffer addresses corresponding to a pixel address space describing spatial positions upon a graphics output device in a computer graphics system or the like, the frame buffer comprising: memory means having K-many separately addressable groups of RAM, each group for reading and writing N-bit words, K being an integer greater than or equal to two and N being an integer greater than or equal to one, the K-many N-bit groups appearing upon a combined data path of (KN)-many bits organized as an ordering by group of the K-many N-bit groups; tile address production means for receiving pixel address having X direction and Y direction components, for receiving a P-many pixel by Q-many pixel tile size specification dividing the pixel address space into contiguous tiles each of (PQ)-many contiguous pixels, P and Q being integers greater than or equal to one, and for producing therefrom a tile address having X direction and Y direction components specifying which tile contains the received pixel address; and frame buffer address production means, coupled to the tile address and to the tile size specification, for producing therefrom K-many addresses, each of which is coupled to an associated one of the K-many separately addressable groups of the memory means, and each of which is a function of the pixel address, the tile size specification and the associated one of the K-many separately addressable groups.

Claim 8

A method of addressing a frame buffer having a plurality of planes, representing a pixel address space and containing multi-bit pixel values, to access in unison a tile of contiguous pluralities of pixels, the method comprising the steps of: a. addressing K-many separately addressable N-bit groups of RAM, each N-bit group for reading and writing N-bit words during K-many simultaneous memory cycles with separate addresses for each N-bit group, K being an integer greater than or equal to two and N being an integer greater than or equal to one, the K-many N-bit groups forming a plane of the multi-plane frame buffer, each such plane having a data path of (KN)-many bits arranged as an ordering by group of the K-many N-bit groups; b. repeating step (a) once for each plane in the frame buffer, there being one such plane for each bit of a multi-bit pixel value; c. forming a tile address including a separate address for each N-bit group, each separate address being a function of at least the pixel address and the N-bit group with which that separate address is associated; and d. for each plane in the frame buffer, performing simultaneous memory cycles upon each N-bit group with the separate addresses of the tile address, whereby a tile of (KN)-many multi-bit pixel values is accessed in the space of a single memory cycle.

Claim 9

A method of addressing a frame buffer having a plurality of planes, representing a pixel address space and containing multi-bit pixel values, to access in unison a tile of contiguous pluralities of pixels, the method comprising the steps of: a. addressing K-many separately addressable N-bit groups of RAM, each N-bit group for reading and writing N-bit words during K-many simultaneous memory cycles with separate addresses for each N-bit group, K being an integer greater than or equal to two and N being an integer greater than or equal to one, the K-many N-bit groups forming a plane of the multi-plane frame buffer, each such plane having a data path of (KN)-many bits arranged as an ordering by group of the K-many N-bit groups; b. repeating step (a) once for each plane in the frame buffer, there being one such plane for each bit of a multi-bit pixel value; c. forming a tile address including a separate address for each N-bit group, each separate address being a function of at least the pixel address and the N-bit group with which that separate address is associated; and d. for each plane in the frame buffer, performing simultaneous memory cycles upon each N-bit group with the separate addresses of the tile address, whereby a tile of (KN)-many multi-bit pixel values is accessed in the space of a single memory cycle.