Patent US5602882A successfully refreshed from Google Patents.
US5602882A
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Digital jitter attenuator using selection of multi-phase clocks and auto-centering elastic buffer
Assignee: Diodes Inc
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Filing: 1996-01-19
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Granted: 1997-02-11
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Expires: 2016-01-19
Abstract
Abstract A jitter attenuator receives data and a receive clock extracted from an input data stream. A transmit clock is generated for retransmitting the data. The transmit clock has less jitter than the receive clock but has the same average frequency. An elastic buffer or FIFO is necessary to buffer the data. The receive clock is divided into a series of write clocks for writing data into the elastic buffer, and the transmit clock is also divided into a series of read clocks for reading data from the elastic buffer. A series of multi-phase clocks is used to generate the transmit clock. The multi-phase clocks all have the same frequency but are offset in phase from one another. A phase selector, under control of a counter, selects one of the multi-phase clocks to be the transmit clock. The counter is incremented or decremented by a phase comparator. The phase comparator compares the phase of one of the write clocks to the phase of one of the read clocks. The counter is incremented when the phase of the write clock lags the read clock, selecting a multi-phase clock with a more retarded phase, but the counter is decremented when the write clock leads the read clock, selecting a multi-phase clock with a more advanced phase. Thus the phase of the transmit clock is adjusted by the phase comparison of the write and read clocks for the elastic buffer. The elastic buffer is forced to half-full by comparing a write and read clock that are separated by half the capacity of the buffer. The phase, rather than the frequency, is adjusted, eliminating the feedback to an external VCO, allowing the jitter attenuator to be integrated on a single silicon substrate.
Inventors
- 👤 Ramon S. Co
- 👤 Lance K. Lee
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 02:22
CPC Classifications
H; H04; H04J; H04J3/00; H04J3/02; H04J3/06; H04J3/062; H04J3/0626; H04L; H04L12/00; H04L12/28; H04L12/42; H04L12/422; H04J3/0632
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
258 words
A method of attenuating jitter from a first clock by buffering and re-transmitting input data with a second clock, the second clock having less jitter than the first clock, the method comprising: receiving the first clock and generating a plurality of write clocks by dividing the first clock, the write clocks having a lower frequency than the first clock, the first clock having a frequency that is a multiple of the frequency of the write clocks; receiving into an elastic buffer the input data at the rate of the first clock and providing from the elastic buffer the input data for re-transmission at the rate of the second clock; receiving the second clock and generating a plurality of read clocks by dividing the second clock, the read clocks having a lower frequency than the second clock, the second clock having a frequency that is a multiple of the frequency of the read clocks; determining the difference in phase between at least one of the plurality of write clocks and at least one of the plurality of read clocks; generating a plurality of multi-phase clocks for generating the second clock; and receiving the plurality of multi-phase clocks and adjusting the phase of the second clock by selecting a clock in the plurality of multi-phase clocks for generating the second clock in response to the difference in phase between at least one of the plurality of write clocks and at least one of the plurality of read clocks, whereby jitter in the first clock is attenuated in the second clock.
Claim 2
Independent Claim
258 words
A method of attenuating jitter from a first clock by buffering and re-transmitting input data with a second clock, the second clock having less jitter than the first clock, the method comprising: receiving the first clock and generating a plurality of write clocks by dividing the first clock, the write clocks having a lower frequency than the first clock, the first clock having a frequency that is a multiple of the frequency of the write clocks; receiving into an elastic buffer the input data at the rate of the first clock and providing from the elastic buffer the input data for re-transmission at the rate of the second clock; receiving the second clock and generating a plurality of read clocks by dividing the second clock, the read clocks having a lower frequency than the second clock, the second clock having a frequency that is a multiple of the frequency of the read clocks; determining the difference in phase between at least one of the plurality of write clocks and at least one of the plurality of read clocks; generating a plurality of multi-phase clocks for generating the second clock; and receiving the plurality of multi-phase clocks and adjusting the phase of the second clock by selecting a clock in the plurality of multi-phase clocks for generating the second clock in response to the difference in phase between at least one of the plurality of write clocks and at least one of the plurality of read clocks, whereby jitter in the first clock is attenuated in the second clock.
Claim 3
Dependent Claim
22 words
The method of claim 1 further comprising: deriving the second clock from an external oscillator, the external oscillator having a constant frequency.
Claim 4
Dependent Claim
218 words
The method of claim 1 further comprising: receiving the at least one of the plurality of write clocks and the at least one of the plurality of read clocks into a phase comparator; generating from the phase comparator an increment signal when the at least one of the plurality of write clocks lags the at least one of the plurality of read clocks in phase, but generating a decrement signal when the at least one of the plurality of write clocks leads the at least one of the plurality of read clocks in phase; transmitting the increment and the decrement signal from the phase comparator to a counter; incrementing in the counter a count value when the increment signal is received but decrementing the count value when the decrement signal is received; outputting the count value from the counter; transmitting the count value from the counter and the plurality of multi-phase clocks to a phase selector; and selecting with the phase selector a selected clock in the plurality of multi-phase clocks in response to the count value from the counter, whereby the phase of the selected clock is adjusted in response to the difference in phase between the at least one of the plurality of write clocks and the at least one of the plurality of read clocks.
Claim 5
Dependent Claim
70 words
The method of claim 3 further comprising: transmitting to an optional divider the selected clock; generating in the optional divider the second clock, the second clock having a lower frequency than the selected clock, the selected clock having a frequency that is a multiple of the frequency of the second clock; and outputting from the optional divider the second clock, whereby the second clock is divided from the selected clock.
Claim 6
Dependent Claim
97 words
The method of claim 3 further comprising: writing a first location in the elastic buffer by the at least one of the plurality of write clocks; and reading a second location by the at least one of the plurality of read clocks, the first location being separated from the second location by substantially half of the storage capacity of the elastic buffer, whereby the elastic buffer is forced into being half-full by the phase comparison of a read clock and a write clock that are separated by substantially half of the storage capacity of the elastic buffer.
Claim 7
Dependent Claim
154 words
The method of claim 5 further comprising: transmitting to a second phase comparator a second one of the plurality of write clocks and a second one of the plurality of read clocks; generating in the second phase comparator a second increment signal when the second one of the plurality of write clocks lags the second one of the plurality of read clocks in phase, but generating a second decrement signal when the second one of the plurality of write clocks leads the second one of the plurality of read clocks in phase; transmitting to the counter the second increment and the second decrement signal from the second phase comparator; incrementing in the counter the count value when the second increment signal is received but decrementing the count value when the second decrement signal is received, whereby the counter is incremented or decremented by two phase comparisons, reducing the degree of jitter attenuation of feedback.
Claim 8
Dependent Claim
327 words
A jitter attenuator, receiving a first clock, the jitter attenuator generating a second clock, the second clock having less jitter than the first clock, the jitter attenuator comprising: input divider means, receiving the first clock, for generating a plurality of write clocks, the write clocks having a lower frequency than the first clock, the first clock having a frequency that is a multiple of the frequency of the write clocks; output divider means, receiving the second clock, for generating a plurality of read clocks, the read clocks having a lower frequency than the second clock, the second clock having a frequency that is a multiple of the frequency of the read clocks; an elastic buffer, receiving input data at the rate of the first clock and providing the input data for re-transmission at the rate of the second clock; a plurality of multi-phase clocks for generating the second clock; and feedback means, receiving the plurality of multi-phase clocks, for adjusting the phase of the second clock by selecting a clock in the plurality of multi-phase clocks for generating the second clock in response to the difference in phase between at least one of the plurality of write clocks and at least one of the plurality of read clocks; phase comparator means, in the feedback means, receiving the at least one of the plurality of write clocks and the at least one of the plurality of read clocks, for generating a decrement signal when the at least one of the plurality of write clocks lags the at least one of the plurality of read clocks in phase, the phase comparator means generating an increment signal when the at least one of the plurality of write clocks leads the at least one of the plurality of read clocks in phase, whereby jitter in the first clock is attenuated in the second clock and whereby the input data is buffered by the elastic buffer and re-transmitted with the second clock.
Claim 9
Dependent Claim
327 words
A jitter attenuator, receiving a first clock, the jitter attenuator generating a second clock, the second clock having less jitter than the first clock, the jitter attenuator comprising: input divider means, receiving the first clock, for generating a plurality of write clocks, the write clocks having a lower frequency than the first clock, the first clock having a frequency that is a multiple of the frequency of the write clocks; output divider means, receiving the second clock, for generating a plurality of read clocks, the read clocks having a lower frequency than the second clock, the second clock having a frequency that is a multiple of the frequency of the read clocks; an elastic buffer, receiving input data at the rate of the first clock and providing the input data for re-transmission at the rate of the second clock; a plurality of multi-phase clocks for generating the second clock; and feedback means, receiving the plurality of multi-phase clocks, for adjusting the phase of the second clock by selecting a clock in the plurality of multi-phase clocks for generating the second clock in response to the difference in phase between at least one of the plurality of write clocks and at least one of the plurality of read clocks; phase comparator means, in the feedback means, receiving the at least one of the plurality of write clocks and the at least one of the plurality of read clocks, for generating a decrement signal when the at least one of the plurality of write clocks lags the at least one of the plurality of read clocks in phase, the phase comparator means generating an increment signal when the at least one of the plurality of write clocks leads the at least one of the plurality of read clocks in phase, whereby jitter in the first clock is attenuated in the second clock and whereby the input data is buffered by the elastic buffer and re-transmitted with the second clock.
Claim 10
Dependent Claim
41 words
The jitter attenuator of claim 7 wherein the plurality of multi-phase clocks for generating the second clock is derived from an external oscillator, the external oscillator having a constant frequency, whereby the feedback means is integrated on a single silicon substrate.
Claim 11
Dependent Claim
138 words
The jitter attenuator of claim 7 wherein the feedback means comprises: counter means, receiving the increment and the decrement signal from the phase comparator means, for incrementing a count value when the increment signal is received but for decrementing the count value when the decrement signal is received, the counter means outputting the count value; and phase selector means, receiving the count value from the counter means and receiving the plurality of multi-phase clocks, the phase selector means selecting a selected clock in the plurality of multi-phase clocks in response to the count value from the counter means, whereby the feedback means adjusts the phase of the selected clock in response to the difference in phase between the at least one of the plurality of write clocks and the at least one of the plurality of read clocks.
Claim 12
Dependent Claim
14 words
The jitter attenuator of claim 9 wherein the selected clock is the second clock.
Claim 13
Dependent Claim
67 words
The jitter attenuator of claim 9 further comprising optional divider means, the optional divider means receiving the selected clock and outputting the second clock, for generating the second clock, the second clock having a lower frequency than the selected clock, the selected clock having a frequency that is a multiple of the frequency of the second clock, whereby the second clock is divided from the selected clock.
Claim 14
Dependent Claim
97 words
The jitter attenuator of claim 9 wherein a first location in the elastic buffer is written by the at least one of the plurality of write clocks; and a second location is read by the at least one of the plurality of read clocks, the first location being separated from the second location by substantially half of the capacity of the elastic buffer, whereby the elastic buffer is forced into being half-full by the phase comparison of a read clock and a write clock that are separated by substantially half of the capacity of the elastic buffer.
Claim 15
Dependent Claim
139 words
The jitter attenuator of claim 8 wherein the feedback means further comprises: counter means, receiving the increment and the decrement signal from the phase comparator means, for incrementing a count value when the increment signal is received but for decrementing the count value when the decrement signal is received, the counter means outputting the count value; and phase selector means, receiving the count value from the counter means and receiving the plurality of multi-phase clocks, the phase selector means selecting a selected clock in the plurality of multi-phase clocks in response to the count value from the counter means, whereby the feedback means adjusts the phase of the selected clock in response to the difference in phase between the at least one of the plurality of write clocks and the at least one of the plurality of read clocks.
References Cited (Backward Citations)
US5162746A
Cited
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-02-11 | 2000-08-12 | 2001-02-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-02-11 | 2004-08-12 | 2005-02-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-02-11 | 2008-08-12 | 2009-02-11 | $7700.00 | Window Closed / Lapsed |