US5162746A — Digitally controlled crystal-based jitter attenua…

Claim 1

Independent Claim 220 words

A jitter attenuator circuit for attenuating phase jitter on an incoming signal, comprising: an oscillator for generating a clock signal at one of N selectable frequencies in response to a digital control signal; first divider means, having an input coupled to an output of the oscillator, for dividing the clock signal by a value C×NB; second divider means, having an input receiving the incoming signal, for dividing the incoming signal by the value NB; a phase detector, having a first input coupled to an output of the first divider means, a second input coupled to an output of the second divider means, and an output coupled to an input of the oscillator, for generating the digital control signal based on a phase relationship between the divided incoming signal and the divided clock signal, wherein the digital control signal selects a frequency f 1 for the clock signal from the N selectable frequencies of the oscillator; said oscillator comprising a dithering means for modulating the clock signal when the frequency of the divided incoming signal is substantially the same as the divided clock signal; the clock signal having a total number T F of selectable frequencies wherein: T.sub.F =(C×NB)×N a selectable resolution R with regard to the frequency of the clock signal: ##EQU10## and an average frequency F avg : ##EQU11##

Claim 2

Dependent Claim 220 words

A jitter attenuator circuit for attenuating phase jitter on an incoming signal, comprising: an oscillator for generating a clock signal at one of N selectable frequencies in response to a digital control signal; first divider means, having an input coupled to an output of the oscillator, for dividing the clock signal by a value C×NB; second divider means, having an input receiving the incoming signal, for dividing the incoming signal by the value NB; a phase detector, having a first input coupled to an output of the first divider means, a second input coupled to an output of the second divider means, and an output coupled to an input of the oscillator, for generating the digital control signal based on a phase relationship between the divided incoming signal and the divided clock signal, wherein the digital control signal selects a frequency f 1 for the clock signal from the N selectable frequencies of the oscillator; said oscillator comprising a dithering means for modulating the clock signal when the frequency of the divided incoming signal is substantially the same as the divided clock signal; the clock signal having a total number T F of selectable frequencies wherein: T.sub.F =(C×NB)×N a selectable resolution R with regard to the frequency of the clock signal: ##EQU10## and an average frequency F avg : ##EQU11##

Claim 3

Dependent Claim 102 words

The jitter attenuator circuit of claim 1, wherein the dithering means comprises: at least one capacitively-loaded amplifier stage comprising an amplifier and one or more capacitors loading an input and output of the amplifier, wherein each stage has an input coupled to an input of a crystal through a first switch and an output coupled to an output of the crystal through a second switch; and means for activating and de-activating both the first and second switches at predetermined intervals, thereby activating and de-activating the capacitively-loaded amplifier stages to prevent the clock signal from locking at one of the N selectable frequencies.

Claim 4

Dependent Claim 103 words

The jitter attenuator circuit of claim 1, wherein the oscillator further comprises: a crystal; one or more capacitively-loaded amplifier stages comprising an amplifier and one or more capacitors loading an input and output of the amplifier, wherein each stage has an input coupled to an input of the crystal through a first switch and an output coupled to an output of the crystal through a second switch; and means for activating and de-activating both the first and second switches, thereby activating and de-activating the capacitively-loaded amplifier stages to alter the load capacitance on the crystal and change the frequency of the clock signal.

Claim 5

Dependent Claim 70 words

The jitter attenuator circuit of claim 3, wherein the digital control signal comprises an N-bit bus, and the means for activating and deactivating comprises means for activating a specified one of the capacitively-loaded amplifier stages whenever a corresponding bit of the N-bit bus is a logical 1, and for deactivating the specified one of the capacitively-loaded amplifier stages whenever the corresponding bit of the N-bit bus is a logical 0.

Claim 6

Dependent Claim 84 words

The jitter attenuator circuit of claim 1, wherein the phase detector comprises: an up/down counter for determining the phase relationship between the divided incoming signal and the divided clock signal, and for producing the digital control signal proportional thereto; means for incrementing and decrementing the up/down counter when the divided clock signal is out of phase with the divided incoming signal; and limiter means for disabling the up/down counter to prevent rollover when a count therein reaches a range boundary for the up/down counter.

Claim 7

Independent Claim 165 words

A method of attentuating phase jitter on an incoming signal, comprising: generating a clock signal at one of N selectable frequencies in response to a digital control signal; dividing the clock signal by a value C×NB; dividing the incoming signal by a value NB; detecting a phase relationship between the divided incoming signal and the divided clock signal; generating the digital control signal based on the detected phase relationship, wherein the digital control signal selects a frequency f i for the clock signal from the N selectable frequencies; and dithering the clock signal when the frequency of the divided incoming signal is substantially the same as the divided clock signal, thereby preventing the clock signal from locking at one of the N selectable frequencies; wherein the method provides a clock signal having a total number T F of selectable frequencies wherein: T.sub.F =(C×NB)×N a selectable resolution R with regard to a frequency of the clock signal: ##EQU12## and an average frequency F avg : ##EQU13##

Claim 8

Independent Claim 165 words

A method of attentuating phase jitter on an incoming signal, comprising: generating a clock signal at one of N selectable frequencies in response to a digital control signal; dividing the clock signal by a value C×NB; dividing the incoming signal by a value NB; detecting a phase relationship between the divided incoming signal and the divided clock signal; generating the digital control signal based on the detected phase relationship, wherein the digital control signal selects a frequency f i for the clock signal from the N selectable frequencies; and dithering the clock signal when the frequency of the divided incoming signal is substantially the same as the divided clock signal, thereby preventing the clock signal from locking at one of the N selectable frequencies; wherein the method provides a clock signal having a total number T F of selectable frequencies wherein: T.sub.F =(C×NB)×N a selectable resolution R with regard to a frequency of the clock signal: ##EQU12## and an average frequency F avg : ##EQU13##

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1995-11-10	1996-05-11	1996-11-10	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	1999-11-10	2000-05-11	2000-11-10	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2003-11-10	2004-05-11	2004-11-10	$7700.00	Window Closed / Lapsed

Digitally controlled crystal-based jitter attenuator

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