Bidirectional electrical overstress protection circuit for bipolar and bipolar-CMOS integrated circuits

Claim 2

An electrical overstress (EOS) protection circuit connected between first and second integrated circuit (IC) terminals, comprising: first and second contra-directed diode-connected bipolar EOS transistors of a first conductivity having emitter, base and collector terminals, connected in series between said first and second IC terminals, one of said EOS transistors having a reverse-biased junction and the other having a forward-biased junction in response to a voltage differential across said IC terminals such that said EOS circuit inhibits current flow between said IC terminals in response to a voltage differential less than the reverse breakdown voltage of said EOS transistor with a reverse-biased junction, and first and second parasitic bipolar transistors of a second conductivity having emitter, base and collector terminals, said parasitic transistors being connected in series to provide a current path between the base terminals of said EOS transistors that actuates the EOS transistor with a reverse-biased junction during an EOS event between said IC terminals.

Claim 3

An EOS protection circuit as in claim 1, wherein said first and second EOS transistors are connected together by their collectors, said first EOS transistor's base and emitter terminals being connected to said first IC terminal and said second EOS transistor's base and emitter terminals being connected to said second IC terminal.

Claim 4

An EOS protection circuit as in claim 2, further comprising a first base-emitter resistor connected between the base and emitter terminals of said first EOS transistor and a second base-emitter resistor connected between the base and emitter terminals of said second EOS transistor, said parasitic transistors providing a current through said base-emitter resistor of the EOS transistor with a reverse-biased junction to turn on said EOS transistor with a reverse-biased junction during an EOS event and activate said EOS protection circuit.

Claim 5

An EOS protection circuit as in claim 2, said circuit providing a holding voltage between said first and second IC terminals during an EOS event, said holding voltage being equal to the sum of the voltage across the base-emitter resistor of the EOS transistor with a forward-biased junction, the collector-to-emitter voltages of said parasitic transistors at saturation and the emitter-to-base voltage of the EOS transistor with a forward-biased junction at saturation.

Claim 6

An EOS protection circuit as in claim 2, wherein one of said IC terminals is a reference voltage terminal.

Claim 7

An EOS protection circuit as in claim 1, wherein said first conductivity is npn and said second conductivity is pnp.

Claim 8

An EOS protection circuit as in claim 1, wherein said first conductivity is pnp and said second conductivity is pnp.

Claim 9

An EOS protection circuit as in claim 1, wherein said collectors of said first and second EOS transistors are connected together and their base and emitter terminals are shorted together and connected to said first and second IC terminals respectively, and one of said IC terminals is a reference voltage terminal.

Claim 10

An electrical overstress (EOS) protection circuit connected between first and second integrated circuit (IC) terminals, comprising: a substrate of a first conductivity type, first and second tubs of a second conductivity type in a surface of said substrate, first and second wells of said first conductivity type inside said first and second tubs respectively, an isolation region in the surface of said substrate between said first and second tubs; first and second regions of said second conductivity type inside said first and second wells, respectively, said first well, said first region, and a portion of said first tub surrounding the first well forming base, emitter and collector terminals, respectively, that define a first diode-connected bipolar EOS transistor, said second well, said second region, and a portion of said second tub surrounding the second well forming base, emitter and collector terminals, respectively, that define a second diode-connected bipolar EOS transistor, said first and second EOS transistors being contra-directed connected in series between said first and second IC terminals, said first well, said first tub, and said isolation region forming a first parasitic bipolar transistor, and said second well, said second tub, and said isolation region forming a second parasitic bipolar transistor, said parasitic transistors providing a current path between said first and second EOS transistors during an EOS event between said IC terminals.

Claim 11

An electrical overstress (EOS) protection circuit connected between first and second integrated circuit (IC) terminals, comprising: a substrate of a first conductivity type, first and second tubs of a second conductivity type in a surface of said substrate, first and second wells of said first conductivity type inside said first and second tubs respectively, an isolation region in the surface of said substrate between said first and second tubs; first and second regions of said second conductivity type inside said first and second wells, respectively, said first well, said first region, and a portion of said first tub surrounding the first well forming base, emitter and collector terminals, respectively, that define a first diode-connected bipolar EOS transistor, said second well, said second region, and a portion of said second tub surrounding the second well forming base, emitter and collector terminals, respectively, that define a second diode-connected bipolar EOS transistor, said first and second EOS transistors being contra-directed connected in series between said first and second IC terminals, said first well, said first tub, and said isolation region forming a first parasitic bipolar transistor, and said second well, said second tub, and said isolation region forming a second parasitic bipolar transistor, said parasitic transistors providing a current path between said first and second EOS transistors during an EOS event between said IC terminals.

Claim 12

An EOS protection circuit as in claim 9, wherein said first and second EOS transistors collector and emitter terminals define respective collector-emitter circuits, said first well is connected to said first region, said second well is connected to said second region, and said first and second tubs are connected to connect the collector-emitter circuits of said first and second EOS transistors together in series between said first and second IC terminals.

Claim 13

An EOS protection circuit as in claim 10, further comprising first and second base-emitter resistors between said base and emitter terminals of said first and second EOS transistors, respectively, said parasitic transistors providing a current through said base-emitter resistor of the EOS transistor with a reverse-biased junction to turn it on during an EOS event and activate said EOS protection circuit.

Claim 14

An EOS protection circuit as in claim 10, wherein said substrate and one of said IC terminals are connected to ground.

Claim 15

An EOS protection circuit as in claim 12, wherein said first and second IC terminals are connected respectively to said first and second tubs, and said first well, first region, second well and second region are connected together.

Claim 16

An EOS protection circuit as in claim 9, wherein said first conductivity is p-type and said second conductivity is n-type.

Claim 17

An EOS protection circuit as in claim 9, wherein said first conductivity is n-type and said second conductivity is p-type.