Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
162 words
A protection circuit against electrostatic discharge (ESD) for complementary metal-oxide-semiconductor (CMOS) integrated circuits (IC) of p-type substrate having n-channel MOS field effect transistors (NMOS) with lightly-doped drain (LDD) and having at least one bonding pad for external connection, comprising: a first n-well having a heavily-doped n+diffusion and a heavily-doped p+diffusion connected together and to said bonding pad, a non-LDD NMOS, which does not have a lightly doped drain, having a drain connected to said first n-well, an n+ source connected to the negative terminal of a power supply with a positive terminal and a negative terminal, a gate connected to said source, and a channel having a effective channel length longer than the channel length of said NMOS with lightly-doped drain (LDD NMOS), said first n-well and said non-LDD NMOS forming a pnpn SCR structure, which turns on when said ESD pulse appears at said bonding pad, with said p+diffusion, said n-well, said p-substrate and said n+source corresponding to said pnpn strusture.
Claim 2
Dependent Claim
162 words
A protection circuit against electrostatic discharge (ESD) for complementary metal-oxide-semiconductor (CMOS) integrated circuits (IC) of p-type substrate having n-channel MOS field effect transistors (NMOS) with lightly-doped drain (LDD) and having at least one bonding pad for external connection, comprising: a first n-well having a heavily-doped n+diffusion and a heavily-doped p+diffusion connected together and to said bonding pad, a non-LDD NMOS, which does not have a lightly doped drain, having a drain connected to said first n-well, an n+ source connected to the negative terminal of a power supply with a positive terminal and a negative terminal, a gate connected to said source, and a channel having a effective channel length longer than the channel length of said NMOS with lightly-doped drain (LDD NMOS), said first n-well and said non-LDD NMOS forming a pnpn SCR structure, which turns on when said ESD pulse appears at said bonding pad, with said p+diffusion, said n-well, said p-substrate and said n+source corresponding to said pnpn strusture.
Claim 3
Dependent Claim
37 words
A protection circuit against ESD as described in claim 1, wherein said bonding pad is connected to the drain of an LDD NMOS output buffer with a source connected to said negative terminal of said power supply.
Claim 4
Dependent Claim
20 words
A protection circuit against ESD as described in claim 1, wherein said non-LDD drain is diffused into said first n-well.
Claim 5
Dependent Claim
23 words
A protection circuit against ESD as described in claim 1, wherein said drain of said LDD MNOS is diffused into said first n-well.
Claim 6
Dependent Claim
28 words
A protection circuit against ESD as described in claim 1, wherein said non-LDD NMOS has a gate oxide as thin as the gate oxide of said LDD NMOS.
Claim 7
Dependent Claim
27 words
A protection circuit against ESD as described in claim 1, wherein said non-LDD NMOS has a gate oxide thicker than the gate oxide of said LDD NMOS.
Claim 8
Dependent Claim
68 words
A protection circuit against ESD as described in claim 1, wherein there is a second n+diffusion, which is diffused outside the non-LDD NMOS away from said first n-well and connected to said positive terminal of said power supply, and forms a first abrupt junction npn bipolar transistor structure corresponding to the second n+diffusion as collector, the p-substrate as base and the n+source of the non-LDD NMOS as emitter.
Claim 9
Dependent Claim
43 words
A protection circuit against ESD as described in claim 7, wherein an oxide with a thickness equal to the gate oxide of the LDD NMOS is interposed over the p-substrate and between said second n+ diffusion and said n+source of said non-LDD NMOS.
Claim 10
Dependent Claim
41 words
A protection circuit ESD as described in claim 7, wherein an oxide with a thickness thicker than the gate oxide of the LDD NMOS is interposed over the p-substrate and between said second n+diffusion and said n+source of said non-LDD NMOS.
Claim 11
Dependent Claim
21 words
A protection circuit against ESD as described in claim 7, wherein there is a second n-well diffused inside said second n+diffusion.
Claim 12
Dependent Claim
58 words
A protection circuit against ESD as described in claim 7, wherein there is a third n+diffusion, which is placed outside said first n-well and connected to said positive terminal of said power supply, and forms a second abrupt junction npn bipolar transistor structure with said third n+diffusion as collector, the p-substrate as base and said n-well as emitter.
Claim 13
Dependent Claim
26 words
A protection circuit against ESD as described in claim 11, wherein the oxide covering said base is as thin as the thickness of the LDD NMOS.
Claim 14
Dependent Claim
26 words
A protection circuit against ESD as described in claim 11, wherein the oxide covering said base is thicker than the gate oxide of the LDD NMOS.
Claim 15
Dependent Claim
21 words
A protection circuit against ESD as described in claim 11, wherein there is a third n-well diffused inside said third n+diffusion.
Claim 16
Dependent Claim
19 words
A protection circuit against ESD as described in claim 1, wherein the n-type and p-type semiconductivity types are reversed.
Claim 17
Dependent Claim
50 words
A protection circuit against ESD as described in claim 8, wherein a polysilicon gate lager is deposited over said oxide which is interposed over said p-substrate and between said second n+diffusion and said n+source diffusion of said said non-LDD NMOS, and connected to said negative terminal of said power supply.