Patent US5600166A successfully refreshed from Google Patents.
US5600166A
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EPROM cell with a readily scalable interpoly dielectric
Assignee: STMicroelectronics SRL
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Filing: 1995-06-01
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Granted: 1997-02-04
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Expires: 2015-06-01
Abstract
Abstract The use of an O--N--RTN (Oxide-Nitride-Rapid Thermal Nitrided Polysilicon) interpoly dielectric multilayer instead of a customary O--N--O (Oxide-Nitride-Oxide) multilayer in the floating gate structure of a progammable, read-only memory cell has beneficial effects on the performance of the cell and facilitates its scaling.
Inventors
- 👤 Cesare Clementi
- 👤 Gabriella Ghidini
- 👤 Marina Tosi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 02:13
CPC Classifications
H; H10; H10D; H10D64/00; H10D64/60; H10D64/66; H10D64/68; H10D64/681; Y; Y10; Y10S; Y10S148/00; Y10S148/114
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
126 words
A programmable nonvolatile read only memory cell having a floating gate of polysilicon to which a control gate is capacitively coupled and electrically isolated therefrom by means of a dielectric multilayer, characterized by the fact that said multilayer consists essentially of: a first nitridized superficial layer of the polysilicon of said floating gate, formed by treatment in a nitrogen atmosphere at a temperature between 900° C. and 1100° C. for between 15 and 150 seconds; a second layer of deposited silicon nitride, over said first nitridized layer of polysilicon; and a third dielectric layer constituted by an oxidized top layer of said deposited second layer of silicon nitride, formed by oxidation in the presence of water vapor at a temperature between 900° C. and 1000° C.
Claim 2
Dependent Claim
126 words
A programmable nonvolatile read only memory cell having a floating gate of polysilicon to which a control gate is capacitively coupled and electrically isolated therefrom by means of a dielectric multilayer, characterized by the fact that said multilayer consists essentially of: a first nitridized superficial layer of the polysilicon of said floating gate, formed by treatment in a nitrogen atmosphere at a temperature between 900° C. and 1100° C. for between 15 and 150 seconds; a second layer of deposited silicon nitride, over said first nitridized layer of polysilicon; and a third dielectric layer constituted by an oxidized top layer of said deposited second layer of silicon nitride, formed by oxidation in the presence of water vapor at a temperature between 900° C. and 1000° C.
Claim 3
Dependent Claim
29 words
A memory as defined in claim 1, wherein said deposited second layer of silicon nitride is less than 15 nanometers thick before said third layer is formed by oxidation.
Claim 4
Dependent Claim
20 words
A memory as defined in claim 1, wherein said third layer has a thickness of between 5 and 20 nanometers.
Claim 5
Dependent Claim
25 words
A nonvolatile read only memory as defined in claim 1, wherein said control gate and floating gate are parts of an electrically programmable memory cell.
Claim 6
Dependent Claim
27 words
A nonvolatile read only memory as defined in claim 1, wherein said control gate and floating gate are parts of an electrically programmable and erasable memory cell.
Claim 7
Dependent Claim
27 words
A nonvolatile read only memory as defined in claim 1, wherein said control gate and floating gate are parts of an electrically programmable and single-bit-erasable memory cell.
Claim 8
Dependent Claim
39 words
A nonvolatile read only memory as defined in claim 1, wherein said first nitridized superficial layer, said second layer of deposited silicon nitride, and said third dielectric layer have a total real thickness in the range of 10-30 nm.
Claim 9
Dependent Claim
25 words
A nonvolatile read only memory as defined in claim 1, wherein said second layer of deposited silicon nitride has a thickness of about 12 nm.
Claim 10
Dependent Claim
22 words
A nonvolatile read only memory as defined in claim 1, wherein said third dielectric layer has a thickness of about 10 nm.
Claim 11
Dependent Claim
39 words
A nonvolatile read only memory as defined in claim 1, wherein said first nitridized superficial layer, said second layer of deposited silicon nitride, and said third dielectric layer have a total real thickness in the range of 10-30 nm.
Claim 12
Dependent Claim
25 words
A nonvolatile read only memory as defined in claim 1, wherein said second layer of deposited silicon nitride has a thickness of about 12 nm.
Claim 13
Dependent Claim
22 words
A nonvolatile read only memory as defined in claim 1, wherein said third dielectric layer has a thickness of about 10 nm.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-02-04 | 2000-08-05 | 2001-02-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-02-04 | 2004-08-05 | 2005-02-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-02-04 | 2008-08-05 | 2009-02-04 | $7700.00 | Window Closed / Lapsed |