Patent US4925593A successfully refreshed from Google Patents.
Patent US5600101A successfully refreshed from Google Patents.
US5600101A
Expired / Lapsed
US
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Multilayer electronic component and method of manufacturing the same
Assignee: Murata Manufacturing Co Ltd
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Filing: 1995-07-20
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Granted: 1997-02-04
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Expires: 2015-07-20
Abstract
Abstract A multilayer electronic component has a substrate having a major surface with an area which can be utilized for mounting another electronic component thereon, and external electrodes arranged with a small pitch. According to a method of manufacturing multilayer electronic components, the external electrodes can be easily formed, and the characteristics of respective multilayer electronic components in the parent laminate can be measured during manufacture. The parent laminate is formed by stacking a plurality of insulating sheets provided with via holes each having a conductor and internal circuits connected to the conductors. V-shaped slits are formed in one of the major surfaces of the parent laminate to divide the via holes and the conductors respectively filled in the via holes and expose the conductors within the slits. The exposed conductors respectively serve as the external electrodes of each of the multilayer electronic components obtained by cutting the parent laminate.
Inventors
- 👤 Norio Sakai
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 02:50
CPC Classifications
H; H01; H01G; H01G4/00; H01G4/002; H01G4/228; H01G4/232; H05; H05K; H05K3/00; H05K3/40; H05K3/403; H10; H10W; H10W70/00; H10W70/60; H10W70/62; H10W70/65; H10W70/657; H05K1/00; H05K1/02; H05K1/09; H05K1/092; H05K2201/00; H05K2201/09; H05K2201/09145; H05K2201/09154; H05K2201/09181; H05K2201/09209; H05K2201/095; H05K2201/09563; H05K3/0011; H05K3/0044; H05K3/0052; H05K3/0097; H05K3/30; H05K3/32; H05K3/34; H05K3/341; H05K3/3431; H05K3/3442; H05K3/4038; H05K3/4053; H05K3/4061; H05K3/4069; Y; Y10; Y10T; Y10T29/00; Y10T29/49; Y10T29/49002; Y10T29/49117; Y10T29/49124; Y10T29/49155; Y10T29/49158; Y10T29/4916; Y10T29/49165
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
55 words
A multilayer electronic component comprising: a substrate having major and side surfaces and comprising a plurality of stacked insulating sheets including an insulating sheet provided with an internal circuit; and an external electrode comprising a conductor applied to an inclined portion formed in said side surface of said substrate and connected to said internal circuit.
Claim 2
Dependent Claim
55 words
A multilayer electronic component comprising: a substrate having major and side surfaces and comprising a plurality of stacked insulating sheets including an insulating sheet provided with an internal circuit; and an external electrode comprising a conductor applied to an inclined portion formed in said side surface of said substrate and connected to said internal circuit.
Claim 3
Dependent Claim
28 words
A multilayer electronic component according to claim 1, wherein said inclined portion has an indentation formed therein, and said external electrode comprises a conductor applied to said indentation.
Claim 4
Dependent Claim
29 words
A multilayer electronic component according to claim 1, wherein said electrode has two ends and both ends of said external electrode are in said inclined portion of said substrate.
Claim 5
Dependent Claim
28 words
A multilayer electronic component according to claim 3, wherein said inclined portion has an indentation formed therein, and said external electrode comprises a conductor applied to said indentation.
Claim 6
Dependent Claim
42 words
A multilayer electronic component according to claim 1, wherein said electrode has two ends and one end of said external electrode is on one of said major surfaces of said substrate, the other end being in said inclined portion of said substrate.
Claim 7
Dependent Claim
28 words
A multilayer electronic component according to claim 5, wherein said inclined portion has an indentation formed therein, and said external electrode comprises a conductor applied to said indentation.
Claim 8
Independent Claim
101 words
A method of manufacturing a multilayer electronic component using a parent laminate formed by stacking a plurality of insulating sheets, including an insulating sheet provided with via holes and an internal circuit, said via holes having respective conductors connected to said internal circuit, said method comprising the steps of: forming a slit which is V-shaped in cross-sectional form in one major surface of said parent laminate to divide said via holes and said conductors and thereby expose said conductors within said slit; and forming a cutting plane continued from said slit to divide said parent laminate and thereby form said component.
Claim 9
Independent Claim
101 words
A method of manufacturing a multilayer electronic component using a parent laminate formed by stacking a plurality of insulating sheets, including an insulating sheet provided with via holes and an internal circuit, said via holes having respective conductors connected to said internal circuit, said method comprising the steps of: forming a slit which is V-shaped in cross-sectional form in one major surface of said parent laminate to divide said via holes and said conductors and thereby expose said conductors within said slit; and forming a cutting plane continued from said slit to divide said parent laminate and thereby form said component.
Claim 10
Dependent Claim
23 words
A method of manufacturing a multilayer electronic component according to claim 7, wherein said conductors comprise conductive material filled into said via holes.
Claim 11
Dependent Claim
30 words
A method of manufacturing a multilayer electronic component according to claim 7, wherein said conductors are films of conductive material respectively formed on inner peripheral surfaces of said via holes.
Claim 12
Independent Claim
126 words
A method of manufacturing a multilayer electronic component using a parent laminate formed by stacking a plurality of insulating sheets including an insulating sheet provided with an internal circuit and via holes, each via hole having a conductor connected to said internal circuit, said method comprising the steps of: stacking at least one additional insulating sheet on one major surface of said laminate, said additional insulating sheet having no via holes or circuits; forming a slit which is V-shaped in cross-sectional form in said one major surface of said parent laminate to divide said via holes and said conductors and thereby expose said conductors within said slit; and forming a cutting plane continued from said slit to divide said parent laminate and thereby form said component.
Claim 13
Independent Claim
126 words
A method of manufacturing a multilayer electronic component using a parent laminate formed by stacking a plurality of insulating sheets including an insulating sheet provided with an internal circuit and via holes, each via hole having a conductor connected to said internal circuit, said method comprising the steps of: stacking at least one additional insulating sheet on one major surface of said laminate, said additional insulating sheet having no via holes or circuits; forming a slit which is V-shaped in cross-sectional form in said one major surface of said parent laminate to divide said via holes and said conductors and thereby expose said conductors within said slit; and forming a cutting plane continued from said slit to divide said parent laminate and thereby form said component.
Claim 14
Dependent Claim
23 words
A method of manufacturing a multilayer electronic component according to claim 10, wherein said conductors comprise conductive material filled into said via holes.
Claim 15
Dependent Claim
30 words
A method of manufacturing a multilayer electronic component according to claim 10, wherein said conductors are films of conductive material respectively formed on inner peripheral surfaces of said via holes.
References Cited (Backward Citations)
US3185947A
Cited
US3964087A
Cited
US4400762A
Cited
US4437141A
Cited
US4821007A
Cited
US4956694A
Cited
US4907128A
Cited
US5060369A
Cited
US5140745A
Cited
US5386087A
Cited
US5276963A
Cited
JPH0696992A
Cited
US5383095A
Cited
US5471368A
Cited
US5486657A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-02-04 | 2000-08-05 | 2001-02-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-02-04 | 2004-08-05 | 2005-02-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-02-04 | 2008-08-05 | 2009-02-04 | $7700.00 | Window Closed / Lapsed |