Patent US2695041A successfully refreshed from Google Patents.
US5598367A
Expired / Lapsed
US
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Trench EPROM
Assignee: International Business Machines Corp
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Filing: 1995-06-07
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Granted: 1997-01-28
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Expires: 2015-06-07
Abstract
Abstract A two-device nonvolatile memory cell is described. The cell comprises a planar FET and a vertical FET in series. The vertical FET has a floating gate that is predominantly capacitively coupled to a buried n well that serves as the control electrode. The structure is very similar to a trench DRAM cell, and the nonvolatile memory cell can be integrated onto a DRAM chip.
Inventors
- 👤 Wendell P. Noble
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 04:21
CPC Classifications
H; H10; H10B; H10B69/00; G; G11; G11C; G11C11/00; G11C11/005; G11C16/00; G11C16/02; G11C16/04; G11C16/0408
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
106 words
A semiconductor chip comprising: a semiconductor substrate having a planar surface and a first substrate region; a first FET having a first gate adjacent a first gate insulator adjacent a first channel in said first substrate region and a first and a second diffused region; and a second FET connected in series with said first FET, said second FET having a second gate adjacent a second gate insulator adjacent a second channel in said first substrate region, said second gate floating and not connected to said first gate, said second gate predominantly capacitively coupled to a control electrode, said control electrode being a third diffused region.
Claim 2
Dependent Claim
106 words
A semiconductor chip comprising: a semiconductor substrate having a planar surface and a first substrate region; a first FET having a first gate adjacent a first gate insulator adjacent a first channel in said first substrate region and a first and a second diffused region; and a second FET connected in series with said first FET, said second FET having a second gate adjacent a second gate insulator adjacent a second channel in said first substrate region, said second gate floating and not connected to said first gate, said second gate predominantly capacitively coupled to a control electrode, said control electrode being a third diffused region.
Claim 3
Dependent Claim
25 words
A semiconductor chip as recited in claim 1, wherein said second FET comprises said second diffused region and said third diffused region, said channel therebetween.
Claim 4
Dependent Claim
15 words
A semiconductor chip as recited in claim 2, wherein said third diffused region is buried.
Claim 5
Dependent Claim
40 words
A semiconductor chip as recited in claim 3, further comprising a trench having a sidewall intersecting said second diffused region and said third diffused region, said first gate being on said planar surface, said second gate being along said sidewall.
Claim 6
Dependent Claim
32 words
A semiconductor chip as recited in claim 1, further comprising a wordline and a bitline, said first gate connected to said word line, said first diffused region connected to said bit line.
Claim 7
Dependent Claim
16 words
A semiconductor chip as recited in claim 1, said chip further comprising a trench DRAM cell.
Claim 8
Dependent Claim
38 words
A semiconductor chip as recited in claim 6, said first FET and said second FET comprising a non-volatile memory cell wherein said non-volatile memory cell and said DRAM memory cell cover substantially equal surface areas on the chip.
Claim 9
Independent Claim
114 words
A method of using an EPROM semiconductor structure comprising the steps of: (a) providing a high voltage on a gate and an intermediate voltage on a first diffusion of a first FET, so as to substantially provide said intermediate voltage on a second diffusion of said first FET; (b) providing a low voltage on a buried plate coupling to a vertical floating gate of a second FET linked in series with said first FET, said vertical floating gate intersecting said second diffusion; and wherein said high, intermediate, and low voltages being sufficient to allow Fowler-Nordheim tunneling of electrons from said floating gate to said second diffusion, leaving said second FET with a reduced Vt.
Claim 10
Independent Claim
114 words
A method of using an EPROM semiconductor structure comprising the steps of: (a) providing a high voltage on a gate and an intermediate voltage on a first diffusion of a first FET, so as to substantially provide said intermediate voltage on a second diffusion of said first FET; (b) providing a low voltage on a buried plate coupling to a vertical floating gate of a second FET linked in series with said first FET, said vertical floating gate intersecting said second diffusion; and wherein said high, intermediate, and low voltages being sufficient to allow Fowler-Nordheim tunneling of electrons from said floating gate to said second diffusion, leaving said second FET with a reduced Vt.
Claim 11
Independent Claim
101 words
A method of providing a flash erase to a plurality of EPROM cells on a semiconductor structure comprising the steps of: (a) providing an intermediate voltage on buried diffusions coupling to floating gates of vertical FETs of the EPROM cells, wherein said floating gates are predominantly capacitively coupled to said buried diffusions; (b) providing a negative voltage on a substrate coupling to all said floating gates; and wherein said intermediate, and negative voltages being sufficient to allow Fowler-Nordheim tunneling of electrons from said substrate to said floating gates if said floating gates had a positive charge, thereby reducing said positive charge.
Claim 12
Independent Claim
101 words
A method of providing a flash erase to a plurality of EPROM cells on a semiconductor structure comprising the steps of: (a) providing an intermediate voltage on buried diffusions coupling to floating gates of vertical FETs of the EPROM cells, wherein said floating gates are predominantly capacitively coupled to said buried diffusions; (b) providing a negative voltage on a substrate coupling to all said floating gates; and wherein said intermediate, and negative voltages being sufficient to allow Fowler-Nordheim tunneling of electrons from said substrate to said floating gates if said floating gates had a positive charge, thereby reducing said positive charge.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-01-28 | 2000-07-29 | 2001-01-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-01-28 | 2004-07-29 | 2005-01-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-01-28 | 2008-07-29 | 2009-01-28 | $7700.00 | Window Closed / Lapsed |