US5598112A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Circuit for generating a demand-based gated clock
Assignee: National Semiconductor Corp
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Filing: 1995-05-26
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Granted: 1997-01-28
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Expires: 2015-05-26
Abstract
Abstract A demand-based clocking circuit generates a demand-based gated clock signal. A latch circuit data input receives an enable signal. A clock input receives a first periodic input clock signal. A latch circuit data output provides a shifted enable signal that transitions from an inactive logic state to an active logic state on the first transition of the first input clock signal from the first to the second logic state after the enable signal transitions from the inactive to the active logic state. The shifted enable signal transitions from the active to the inactive logic state on the first transition of the first input clock signal from the first to the second logic state after the enable signal transitions from the active to the inactive logic state. A logic circuit provides the gated clock signal such that the gated clock signal transitions from the inactive to the active logic state on the first transition of a second input clock signal from the first to the second logic state after the shifted enable signal transitions from the inactive to the active logic state, and that transitions from the active to the inactive logic state on the transition of the shifted enable signal from the active to the inactive logic state.
Inventors
- 👤 Christopher E. Phillips
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 16:04
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/13; H03K5/135
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
332 words
A demand-based clocking circuit for generating a demand-based gated clock signal, the clocking circuit comprising: a latch circuit having a data output, a data input connected to receive an enable signal having an active logic state and an inactive logic state, and a clock input connected to receive a first input clock signal having periodic clock cycles wherein, in each of said clock cycles, the first input clock signal has a first logic state during a first portion of the clock cycle and transitions to a second logic state during a second portion of the clock cycle, the data output being connected to provide a shifted enable signal that transitions from the inactive logic state to the active logic state on the first transition of the first input clock signal from the first to the second logic state after the enable signal transitions from the inactive to the active logic state, and that transitions from the active to the inactive logic state on the first transition of the first input clock signal from the first to the second logic state after the enable signal transitions from the active to the inactive logic state; and a logic circuit responsive to the shifted enable signal and to a second input clock signal having periodic clock cycles wherein, in each of said clock cycles, the second input clock signal has the second logic state during a first portion of the cycle and transitions to the first logic state during a second portion of the cycle, for providing the gated clock signal such that the gated clock signal transitions from the inactive to the active logic state on the first transition of the second input clock signal from the first to the second logic state after the shifted enable signal transitions from the inactive to the active logic state, and that transitions from the active to the inactive logic state on the transition of the shifted enable signal from the active to the inactive logic state.
Claim 2
Dependent Claim
332 words
A demand-based clocking circuit for generating a demand-based gated clock signal, the clocking circuit comprising: a latch circuit having a data output, a data input connected to receive an enable signal having an active logic state and an inactive logic state, and a clock input connected to receive a first input clock signal having periodic clock cycles wherein, in each of said clock cycles, the first input clock signal has a first logic state during a first portion of the clock cycle and transitions to a second logic state during a second portion of the clock cycle, the data output being connected to provide a shifted enable signal that transitions from the inactive logic state to the active logic state on the first transition of the first input clock signal from the first to the second logic state after the enable signal transitions from the inactive to the active logic state, and that transitions from the active to the inactive logic state on the first transition of the first input clock signal from the first to the second logic state after the enable signal transitions from the active to the inactive logic state; and a logic circuit responsive to the shifted enable signal and to a second input clock signal having periodic clock cycles wherein, in each of said clock cycles, the second input clock signal has the second logic state during a first portion of the cycle and transitions to the first logic state during a second portion of the cycle, for providing the gated clock signal such that the gated clock signal transitions from the inactive to the active logic state on the first transition of the second input clock signal from the first to the second logic state after the shifted enable signal transitions from the inactive to the active logic state, and that transitions from the active to the inactive logic state on the transition of the shifted enable signal from the active to the inactive logic state.
Claim 3
Dependent Claim
34 words
A demand-based clock circuit as in claim 1, wherein the periodic clock cycles of the first input clock signal have a same duration as the periodic clock cycles of the second input clock signal.
Claim 4
Dependent Claim
25 words
A demand-based clock circuit as in claim 2, wherein the first input clock signal is 180° out of phase from the second input clock signal.
Claim 5
Dependent Claim
38 words
A demand-based clock circuit as in claim 1, wherein the transitions of the first clock signal from the first logic state to the second logic state occur only when the second clock signal has the second logic state.
Claim 6
Dependent Claim
17 words
A demand-based clock circuit as in claim 1, wherein the latch circuit is a D-type flip flop.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-01-28 | 2000-07-29 | 2001-01-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-01-28 | 2004-07-29 | 2005-01-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-01-28 | 2008-07-29 | 2009-01-28 | $7700.00 | Window Closed / Lapsed |