Method and apparatus for indicating the severity of a fault within a computer system

Claim 2

In an electrical apparatus having a plurality of hardware elements and a number of error detection circuits, the number of error detection circuits being coupled to predetermined ones of the plurality of hardware elements, each of the number of error detection circuits continuously monitoring a corresponding one of the predetermined ones of the plurality of hardware elements and providing a corresponding error bit whenever an error is detected thereby, each of the corresponding error bits being serviced by a support controller, the improvement of the electrical apparatus comprising: a. receiving means coupled to at least one of the number of error detection circuits for receiving a corresponding error bit from each of said at least one of the number of error detection circuits; and b. determining means coupled to said receiving means for determining which of the corresponding error bits provided by said at least one of the number of error detection circuits are to be serviced immediately by the support controller, and which of the corresponding error bits provided by said at least one of the number of error detection circuits are to be serviced at a predetermined time later by the support controller.

Claim 3

An electrical apparatus according to claim 1 wherein a first subset of the number of error detection circuits are associated with a first group and a second subset of the number of error detection circuits are associated with a second group, said determining means allowing each of the number of error detection circuits associated with said first group to be serviced by the support controller at a first predetermined time, and said determining means allowing each of the number of error detection circuits associated with said second group to be serviced by the support controller at a second predetermined time.

Claim 4

An electrical apparatus according to claim 2 wherein said receiving means comprises a number of error detection registers.

Claim 5

A data processing system for executing a number of sequential instructions including a current instruction, comprising: a. a first group of hardware elements and a second group of hardware elements wherein said first group of hardware elements further includes a first error detecting means and said second group of hardware elements further includes a second error detection means, said first error detection means continuously monitoring preselected ones of said first group of hardware elements and detecting a number of predefined errors in the preselected ones of said first group of hardware elements, and said second error detecting means continuously monitoring predefined ones of said second group of hardware elements and detecting a number of predefined errors in the preselected ones of said second group of hardware elements; and b. servicing means coupled to said first group of hardware element and to said second group of hardware elements for servicing said number of predefined errors detected by said first error detecting means and said number of predefined errors detected by said second error detecting means, said servicing means servicing said predefined errors detected in said first group of hardware elements before servicing said predefined errors detected in said second group of hardware elements.

Claim 6

A data processing system for executing a number of sequential instructions including a current instruction, comprising: a. a first group of hardware elements and a second group of hardware elements wherein said first group of hardware elements further includes a first error detecting means and said second group of hardware elements further includes a second error detection means, said first error detection means continuously monitoring preselected ones of said first group of hardware elements and detecting a number of predefined errors in the preselected ones of said first group of hardware elements, and said second error detecting means continuously monitoring predefined ones of said second group of hardware elements and detecting a number of predefined errors in the preselected ones of said second group of hardware elements; and b. servicing means coupled to said first group of hardware element and to said second group of hardware elements for servicing said number of predefined errors detected by said first error detecting means and said number of predefined errors detected by said second error detecting means, said servicing means servicing said predefined errors detected in said first group of hardware elements before servicing said predefined errors detected in said second group of hardware elements.

Claim 7

A data processing system according to claim 4 wherein said servicing means services said predefined errors detected in said first group of hardware elements immediately and services said predefined errors detected in said second group of hardware elements at a predetermined time later.

Claim 8

A data processing system according to claim 5 wherein said servicing means further includes interrupting means, wherein said interrupting means interrupts the execution of the data processing system before said servicing means services said predefined errors detected in said first group of hardware elements.

Claim 9

A data processing system according to claim 6 wherein said servicing means further includes determining means for determining when the execution of the current instruction is complete, and control means coupled to said determining means for controlling when said servicing means services said predefined errors detected in said second group of hardware elements, said control means prompting said servicing means to service said predefined errors detected in said second group of hardware elements after the execution of the current instruction is completed.

Claim 10

A data processing system according to claim 6 wherein a utilization factor is defined by the number of sequential instructions executed by the data processing system per unit time, said servicing means further including control means wherein said control means prompts said servicing means to service said predefined errors detected in said second group of hardware elements after said utilization factor of the data processing system drops below a predetermined level.

Claim 11

A data processing system according to claim 6 wherein said servicing means further includes determining means for determining when the data processing system is rebooted, and control means coupled to said determining means for controlling when said servicing means services said predefined errors detected in said second group of hardware elements, said control means prompting said servicing means to service said predefined errors detected in said second group of hardware elements during the next reboot of the data processing system.

Claim 12

A data processing system according to claim 6 wherein said servicing means further includes means for notifying a service technician of said predefined errors detected in said second group of hardware elements for a next preventive maintenance session.

Claim 13

A data processing system according to claim 5 wherein said predefined errors detected in said first group of hardware elements are critical errors.

Claim 14

A data processing system according to claim 5 wherein said predefined errors detected in said second group of hardware elements are passive errors.

Claim 15

A data processing system for executing a number of sequential instructions including a current instruction, comprising: a. a support controller; b. a first group of hardware element; c. a number of first error detecting means coupled to preselected ones of said first group of hardware elements, said number of first error detecting means for continuously monitoring the preselected ones of said first group of hardware elements and detecting a number of corresponding first errors in said preselected ones of said first group of hardware elements; d. first error storage means coupled to said number of first error detecting means for storing said number of corresponding first errors; e. first disabling means coupled to said first error storage means for disabling said first error storage means once a first one of said number of corresponding first errors is detected; f. first providing means coupled to said first error storage means and further coupled to said support controller for providing a first fault type to said support controller when said first one of said number of corresponding first errors is detected; g. a second group of hardware elements; h. a number of second error detecting means coupled to preselected ones of said second group of hardware elements, said number of second error detecting means for continuously monitoring the preselected ones of said second group of hardware elements and detecting a number of corresponding second errors in said preselected ones of said second group of hardware elements; i. second error storage means coupled to said number of second error detecting means for storing said number of corresponding second errors; j. second disabling means coupled to said second error storage means for disabling said second error storage means once a first one of said number of corresponding second errors is detected; k. second providing means coupled to said second error storage means and further coupled to said support controller for providing a second fault type to said support controller when the first one of said number of corresponding second errors is detected; and l. servicing means coupled to said support controller wherein said servicing means services said first fault type before servicing said second fault type.

Claim 16

A data processing system for executing a number of sequential instructions including a current instruction, comprising: a. a support controller; b. a first group of hardware element; c. a number of first error detecting means coupled to preselected ones of said first group of hardware elements, said number of first error detecting means for continuously monitoring the preselected ones of said first group of hardware elements and detecting a number of corresponding first errors in said preselected ones of said first group of hardware elements; d. first error storage means coupled to said number of first error detecting means for storing said number of corresponding first errors; e. first disabling means coupled to said first error storage means for disabling said first error storage means once a first one of said number of corresponding first errors is detected; f. first providing means coupled to said first error storage means and further coupled to said support controller for providing a first fault type to said support controller when said first one of said number of corresponding first errors is detected; g. a second group of hardware elements; h. a number of second error detecting means coupled to preselected ones of said second group of hardware elements, said number of second error detecting means for continuously monitoring the preselected ones of said second group of hardware elements and detecting a number of corresponding second errors in said preselected ones of said second group of hardware elements; i. second error storage means coupled to said number of second error detecting means for storing said number of corresponding second errors; j. second disabling means coupled to said second error storage means for disabling said second error storage means once a first one of said number of corresponding second errors is detected; k. second providing means coupled to said second error storage means and further coupled to said support controller for providing a second fault type to said support controller when the first one of said number of corresponding second errors is detected; and l. servicing means coupled to said support controller wherein said servicing means services said first fault type before servicing said second fault type.

Claim 17

A data processing system according to claim 13 wherein said servicing means further includes means for prioritizing said first fault type and said second fault type such that said servicing means services said first fault type immediately and services said second fault type at a predetermined time later.

Claim 18

A data processing system according to claim 14 wherein said servicing means further includes interrupting means, said interrupting means interrupts the execution of the data processing system before said servicing means services said first fault type.

Claim 19

A data processing system according to claim 14 wherein said servicing means further includes determining means for determining when the execution of the current instruction is complete, and control means coupled to said determining means for controlling when said servicing means services said second fault type, said control means prompting said servicing means to service said second fault type after the execution of the current instruction is completed.

Claim 20

A data processing system according to claim 14 wherein a utilization factor is defined by the number of sequential instructions executed by the data processing system per unit time, said servicing means further includes control means for controlling when said servicing means services said second fault type, said control means prompting said servicing means to service said second fault type after said utilization factor of the data processing system drops below a predetermined level.

Claim 21

A data processing system according to claim 14 wherein said servicing means further includes determining means for determining when the data processing is rebooted, and control means coupled to said determining means for controlling when said servicing means services said second fault type, said control means prompting said servicing means to service said second fault type during the next reboot of the data processing system.

Claim 22

A data processing system according to claim 14 wherein said servicing means further includes means for notifying a service technician of said second fault type for a next preventive maintenance session.

Claim 23

A data processing system according to claim 13 wherein said first fault type corresponds to a critical error.

Claim 24

A data processing system according to claim 20 wherein said second fault type corresponds to a passive error.

Claim 25

A data processing system according to claim 21 wherein each of said number of first error detecting means comprise a parity checking circuit.

Claim 26

A data processing system according to claim 22 wherein each of said number of second error detecting means comprise a parity checking circuit.

Claim 27

In an electrical apparatus having a plurality of hardware elements and a number of error detection circuits, the number of error detection circuits being coupled to predetermined ones of the plurality of hardware elements, each of the number of error detection circuits continuously monitoring a corresponding one of the predetermined ones of the plurality of hardware elements and providing a corresponding error bit whenever an error is detected thereby, each of the corresponding error bits being serviced by a support controller, the improvement of the electrical apparatus comprising: a. a receiving circuit coupled to at least one of the number of error detection circuits for receiving a corresponding error bit from each of said at least one of the number of error detection circuits; and b. determining circuit coupled to said receiving circuit for determining which of the corresponding error bits provided by said at least one of the number of error detection circuits are to be serviced immediately by the support controller, and which of the corresponding error bits provided by said at least one of the number of error detection circuits are to be serviced at a predetermined time later by the support controller.

Claim 28

In an electrical apparatus having a plurality of hardware elements and a number of error detection circuits, the number of error detection circuits being coupled to predetermined ones of the plurality of hardware elements, each of the number of error detection circuits continuously monitoring a corresponding one of the predetermined ones of the plurality of hardware elements and providing a corresponding error bit whenever an error is detected thereby, each of the corresponding error bits being serviced by a support controller, the improvement of the electrical apparatus comprising: a. a receiving circuit coupled to at least one of the number of error detection circuits for receiving a corresponding error bit from each of said at least one of the number of error detection circuits; and b. determining circuit coupled to said receiving circuit for determining which of the corresponding error bits provided by said at least one of the number of error detection circuits are to be serviced immediately by the support controller, and which of the corresponding error bits provided by said at least one of the number of error detection circuits are to be serviced at a predetermined time later by the support controller.

Claim 29

An electrical apparatus according to claim 24 wherein a first subset of the number of error detection circuits are associated with a first group and a second subset of the number of error detection circuits are associated with a second group, said determining circuit allowing each of the number of error detection circuits associated with said first group to be serviced by the support controller at a first predetermined time, and said determining circuit allowing each of the number of error detection circuits associated with said second group to be serviced by the support controller as a second predetermined time.

Claim 30

An electrical apparatus according to claim 25 wherein said receiving circuit comprises a number of error detection registers.

Claim 31

A data processing system for executing a number of sequential instructions including a current instruction, comprising: a. a first group of hardware elements and a second group of hardware elements wherein said first group of hardware elements further includes a first error detecting circuit and said second group of hardware elements further includes a second error detection circuit, said first error detection circuit continuously monitoring preselected ones of said first group of hardware elements and detecting a number of predefined errors in the preselected ones of said first group of hardware elements each of said, and said second error detecting circuit continuously monitoring preselected ones of said second group of hardware elements and detecting a number of predefined errors in the preselected ones of said second group of hardware elements; and b. a servicing circuit coupled to said first group of hardware element and to said second group of hardware elements for servicing said number of predefined errors detected by said first error detecting circuit and said number of predefined errors detected by said second error detecting circuit, said servicing circuit servicing said predefined errors detected in said first group of hardware elements before servicing said predefined errors detected in said second group of hardware elements.

Claim 32

A data processing system for executing a number of sequential instructions including a current instruction, comprising: a. a first group of hardware elements and a second group of hardware elements wherein said first group of hardware elements further includes a first error detecting circuit and said second group of hardware elements further includes a second error detection circuit, said first error detection circuit continuously monitoring preselected ones of said first group of hardware elements and detecting a number of predefined errors in the preselected ones of said first group of hardware elements each of said, and said second error detecting circuit continuously monitoring preselected ones of said second group of hardware elements and detecting a number of predefined errors in the preselected ones of said second group of hardware elements; and b. a servicing circuit coupled to said first group of hardware element and to said second group of hardware elements for servicing said number of predefined errors detected by said first error detecting circuit and said number of predefined errors detected by said second error detecting circuit, said servicing circuit servicing said predefined errors detected in said first group of hardware elements before servicing said predefined errors detected in said second group of hardware elements.

Claim 33

A data processing system according to claim 27 wherein said servicing circuit services said predefined errors detected in said first group of hardware elements immediately and services said predefined errors detected in said second group of hardware elements at a predetermined time later.

Claim 34

A data processing system according to claim 28 wherein said servicing circuit further includes an interrupting circuit, wherein said interrupting circuit interrupts the execution of the data processing system before said servicing means services said predefined errors detected in said first group of hardware elements.

Claim 35

A data processing system according to claim 29 wherein said servicing circuit further includes a determining circuit for determining when the execution of the current instruction is complete, and a control circuit coupled to said determining circuit for controlling when said servicing circuit services said predefined errors detected in said second group of hardware elements, said control circuit prompting said servicing circuit to service said predefined errors detected in said second group of hardware elements after the execution of the current instruction is completed.

Claim 36

A data processing system according to claim 29 wherein a utilization factor is defined by the number of sequential instructions executed by the data processing system per unit time, said servicing circuit further including a control circuit wherein said control circuit prompts said servicing circuit to service said predefined errors detected in said second group of hardware elements after said utilization factor of the data processing system drops below a predetermined level.

Claim 37

A data processing system according to claim 29 wherein said servicing circuit further includes a determining circuit for determining when the data processing system is rebooted, and a control circuit coupled to said determining circuit for controlling when said servicing circuit services said predefined errors detected in said second group of hardware elements, said control circuit prompting said servicing circuit to service said predefined errors detected in said second group of hardware elements during the next reboot of the data processing system.

Claim 38

A data processing system according to claim 29 wherein said servicing circuit further includes a notifying circuit for notifying a service technician of said predefined errors detected in said second group of hardware elements for a next preventive maintenance session.

Claim 39

A data processing system according to claim 28 wherein said predefined errors detected in said first group of hardware elements are critical errors.

Claim 40

A data processing system according to claim 28 wherein said predefined errors detected in said second group of hardware elements are passive errors.

Claim 41

A data processing system for executing a number of sequential instructions including a current instruction, comprising: a. a support controller; b. a first group of hardware elements; c. a number of first error detecting circuits coupled to preselected ones of said first group of hardware elements, said number of first error detecting circuits for continuously monitoring a corresponding one of the preselected ones of said first group of hardware elements and detecting a number of corresponding first errors in said preselected ones of said first group of hardware elements; d. a first error storage circuit coupled to said number of first error detecting circuits for storing said number of corresponding first errors; e. a first disabling circuit coupled to said first error storage circuit for disabling said first error storage circuit once a first one of said number of corresponding first errors is detected; f. a first providing circuit coupled to said first error storage circuit and further coupled to said support controller for providing a first fault type to said support controller when said first one of said number of corresponding first errors is detected; g. a second group of hardware elements; h. a number of second error detecting circuits coupled to preselected ones of said second group of hardware elements, said number of second error detecting circuits for continuously monitoring a corresponding one of the preselected ones of said second group of hardware elements and detecting a number of corresponding second errors in said preselected ones of said second group of hardware elements; i. a second error storage circuit coupled to said number of second error detecting circuit for storing said number of corresponding second errors; j. a second disabling circuit coupled to said second error storage circuit for disabling said second error storage circuit once a first one of said number of corresponding second errors is detected; k. a second providing circuit coupled to said second error storage circuit and further coupled to said support controller for providing a second fault type to said support controller when the first one of said number of corresponding second errors is detected; and l. a servicing circuit coupled to said support controller wherein said servicing circuit services said first fault type before servicing said second fault type.

Claim 42

A data processing system for executing a number of sequential instructions including a current instruction, comprising: a. a support controller; b. a first group of hardware elements; c. a number of first error detecting circuits coupled to preselected ones of said first group of hardware elements, said number of first error detecting circuits for continuously monitoring a corresponding one of the preselected ones of said first group of hardware elements and detecting a number of corresponding first errors in said preselected ones of said first group of hardware elements; d. a first error storage circuit coupled to said number of first error detecting circuits for storing said number of corresponding first errors; e. a first disabling circuit coupled to said first error storage circuit for disabling said first error storage circuit once a first one of said number of corresponding first errors is detected; f. a first providing circuit coupled to said first error storage circuit and further coupled to said support controller for providing a first fault type to said support controller when said first one of said number of corresponding first errors is detected; g. a second group of hardware elements; h. a number of second error detecting circuits coupled to preselected ones of said second group of hardware elements, said number of second error detecting circuits for continuously monitoring a corresponding one of the preselected ones of said second group of hardware elements and detecting a number of corresponding second errors in said preselected ones of said second group of hardware elements; i. a second error storage circuit coupled to said number of second error detecting circuit for storing said number of corresponding second errors; j. a second disabling circuit coupled to said second error storage circuit for disabling said second error storage circuit once a first one of said number of corresponding second errors is detected; k. a second providing circuit coupled to said second error storage circuit and further coupled to said support controller for providing a second fault type to said support controller when the first one of said number of corresponding second errors is detected; and l. a servicing circuit coupled to said support controller wherein said servicing circuit services said first fault type before servicing said second fault type.

Claim 43

A data processing system according to claim 36 wherein said servicing circuit further includes a control circuit wherein said control circuit ensures that said servicing circuit services said first fault immediately and services said second fault type at a predetermined time later.

Claim 44

A data processing system according to claim 37 wherein said servicing circuit further includes an interrupting circuit, said interrupting circuit interrupts the execution of the data processing system before said servicing circuit services said first fault type.

Claim 45

A data processing system according to claim 38 wherein said servicing circuit further includes a determining circuit for determining when the execution of the current instruction is complete, and a control circuit coupled to said determining circuit for controlling when said servicing circuit services said second fault type, said control circuit prompting said servicing circuit to service said second fault type after the execution of the current instruction is completed.

Claim 46

A data processing system according to claim 38 wherein a utilization factor is defined by the number of sequential instructions executed by the data processing system per unit time, said servicing circuit further includes a control circuit for controlling when said servicing circuit services said second fault type, said control circuit prompting said servicing circuit to service said second fault type after said utilization factor of the data processing system drops below a predetermined level.

Claim 47

A data processing system according to claim 38 wherein said servicing circuit further includes a determining circuit for determining when the data processing is rebooted, and a control circuit coupled to said determining circuit for controlling when said servicing circuit services said second fault type, said control circuit prompting said servicing circuit to service said second fault type during the next reboot of the data processing system.

Claim 48

A data processing system according to claim 38 wherein said servicing circuit further includes a notifying circuit for notifying a service technician of said second fault type for a next preventive maintenance session.

Claim 49

A data processing system according to claim 36 wherein said first fault type correspond to a critical error.

Claim 50

A data processing system according to claim 43 wherein said second fault type corresponds to a passive error.

Claim 51

A data processing system according to claim 44 wherein each of said number of first error detecting circuits comprise a parity checking circuit.

Claim 52

A data processing system according to claim 45 wherein each of said number of second error detecting circuits comprise a parity checking circuit.