Burst address sequence generator for addressing static random-access-memory devices

Claim 1

A burst address sequence generator for a static random-access-memory device, comprising: a counter, controlled by a mode signal, the counter including: a first multiplexer, controlled by an inverse signal of said mode signal, driven by a first clock signal, for outputting a signal which is either an external address signal or a zero value; a first flip-flop, preset by the output signal of said first multiplexer, driven by a second clock signal, for outputting a count value; a second multiplexer, controlled by said inverse signal of said mode signal, driven by said first clock signal, for outputting a signal which is either the external address signal or a zero value; a second flip-flop, preset by the output signal of said second multiplexer, driven by said second clock signal, for outputting a count value, an inverse output end of the second flip-flop being connected to an input end thereof, and a counter exclusive-OR gate, receiving said count values of said first flip-flop and said second flip-flop for providing an output to the input end of said first flip-flop; a latch, controlled by said mode signal, the latch including a third multiplexer, controlled by said mode signal, outputting a signal selected from said external address signal and a zero value; a third flip-flop, receiving the output signal of said third multiplexer, driven by an inverse signal of said first clock signal, for generating a pre-address signal; a fourth multiplexer, controlled by said mode signal, outputting a signal selected from said external address signal and a zero value; and a fourth flip-flop, receiving the output signal of said fourth multiplexer, driven by said inverse signal of said first clock signal, for generating a pre-address signal; and a generator exclusive-OR gate, receiving said count values and said pre-address signals, for generating a burst address sequence.