Nonvolatile semiconductor memory device

Claim 2

A nonvolatile semiconductor memory device comprising: a semiconductor substrate with an element region and a field region; a select MOS transistor formed in said element region; and a data storage MOS transistor which is formed in said element region and which includes a source region, a drain region, a floating-gate electrode, and a control gate electrode, said floating-gate electrode having a first portion above said drain region and a second portion above said semiconductor substrate between said source region and said drain region, an insulating film thinner than a gate insulating film of said select MOS transistor being arranged between said drain region and said first portion of said floating-gate electrode and between said semiconductor substrate and said second portion of said floating-gate electrode, and said first and second portions of said floating-gate electrode being spaced apart above said element region, and connected to each other on said field region.

Claim 3

A nonvolatile semiconductor memory device according to claim 1, wherein said drain region of said data storage MOS transistor includes: a first drain region portion arranged in a region including a place directly under said first portion of said floating-gate electrode, and a first side of which is under the space between said first and second portions of said floating-gate electrode; and a second drain region portion, a first side of which is placed on the side of said second portion of said floating-gate electrode, and a second side of which is connected to said first side of said first drain region portion, said second drain region portion having an impurity concentration which is set at least several times lower than the impurity concentration of said first drain region portion.

Claim 4

A nonvolatile semiconductor memory device according to claim 2, wherein said drain region of said data storage MOS transistor further includes a third drain region portion, a first side of which is connected to the second side of said first region, and a second side of which is placed on the side of a gate electrode of said select MOS transistor.

Claim 5

A nonvolatile semiconductor memory device according to claim 3, wherein the impurity concentration in said second drain region portion is equal to the impurity concentration in said third drain region portion.

Claim 6

A nonvolatile semiconductor memory device according to claim 3, wherein said first, second and third drain region portions also function as a source region of said select MOS transistor.

Claim 7

A nonvolatile semiconductor memory device according to claim 5, wherein the impurity concentration of said first drain region portion and that in said second drain region portion are set so that, when a positive potential is applied to said drain region of said data storage MOS transistor and a ground potential to said control gate electrode, a current starts to flow from said drain region of said data storage MOS transistor to said floating-gate electrode before a current starts to flow from said drain region of said data storage MOS transistor to said semiconductor substrate.

Claim 8

A nonvolatile semiconductor memory device according to claim 2, wherein said first drain region portion includes impurities of more than two types whose diffusion coefficient differs from each other, with the impurities whose diffusion coefficient is lower than the remaining ones of said impurities of more than two types determining the impurity concentration at the surface of said drain region of said data storage MOS transistor, and the impurities whose diffusion coefficient is higher than the remaining ones of said impurities of more than two types extending to directly under said field region.

Claim 9

A nonvolatile semiconductor memory device according to claim 7, wherein said impurities of more than two types whose diffusion coefficient differs from each other contain arsenic and phosphorus.

Claim 10

A nonvolatile semiconductor memory device according to claim 1, wherein said insulating film between said drain region and said first portion of said floating-gate electrode functions as a tunnel insulating film through which Fowler-Nordheim tunneling current flows, and said insulating film between said semiconductor substrate and said second portion of said floating-gate electrode functions as a gate insulating film of said data storage MOS transistor and as a tunnel insulating film.

Claim 11

A nonvolatile semiconductor memory device according to claim 1, wherein said insulating film between said drain region and said first portion of said floating-gate electrode and that between said semiconductor substrate and said second portion of said floating-gate electrode has a thickness of approximately 10 nm, and the gate insulating film of said select MOS transistor has a thickness of several tens nm.

Claim 12

A nonvolatile semiconductor memory device according to claim 1, wherein in said element region, the shape of said control gate electrode is the same as that of said floating-gate electrode.

Claim 13

A semiconductor memory device including a memory cell having a selection transistor and a data storage transistor, comprising: a semiconductor substrate of a first conductivity type; a field insulating film formed on said semiconductor substrate to define an element region; first, second, and third impurity regions of a second conductivity type formed in said element region of said semiconductor substrate; a gate electrode of said selection transistor provided above a first channel region between said first and second impurity regions; a floating gate electrode of said data storage transistor having a first electrode portion provided over at least a portion of said second impurity region, and a second electrode portion, spaced apart from said first electrode portion, provided over a second channel region between said second impurity region and said third impurity region; a first insulating film formed between said first electrode portion of said floating gate electrode and said at least a portion of said second impurity region and between said second electrode portion of said floating gate electrode and said second channel region; and a second insulating film formed between said gate electrode of said selection transistor and said first channel region, wherein the thickness of said first insulating film is less than the thickness of said second insulating film.

Claim 14

A semiconductor memory device including a memory cell having a selection transistor and a data storage transistor, comprising: a semiconductor substrate of a first conductivity type; a field insulating film formed on said semiconductor substrate to define an element region; first, second, and third impurity regions of a second conductivity type formed in said element region of said semiconductor substrate; a gate electrode of said selection transistor provided above a first channel region between said first and second impurity regions; a floating gate electrode of said data storage transistor having a first electrode portion provided over at least a portion of said second impurity region, and a second electrode portion, spaced apart from said first electrode portion, provided over a second channel region between said second impurity region and said third impurity region; a first insulating film formed between said first electrode portion of said floating gate electrode and said at least a portion of said second impurity region and between said second electrode portion of said floating gate electrode and said second channel region; and a second insulating film formed between said gate electrode of said selection transistor and said first channel region, wherein the thickness of said first insulating film is less than the thickness of said second insulating film.

Claim 15

A semiconductor memory device according to claim 12, wherein the thickness of said first insulating film is approximately 10 nanometers and the thickness of said second insulating film is approximately several tens of nanometers.

Claim 16

A semiconductor memory device according to claim 12, wherein said second impurity region includes a first impurity region portion arranged between second and third impurity region portions.

Claim 17

A semiconductor memory device according to claim 14, wherein a junction between said first impurity region portion and said second impurity region portion is below the space between said first and second electrode portions of said floating gate electrode.

Claim 18

A semiconductor memory device according to claim 15, wherein a junction between said second impurity region portion and said semiconductor substrate is below an edge of the second electrode portion of said floating gate electrode.

Claim 19

A semiconductor memory device according to claim 15, wherein the impurity concentration of said second impurity region portion is less than the impurity concentration of said first impurity region portion.

Claim 20

A semiconductor memory device according to claim 17, wherein the impurity concentration of said third impurity region portion is approximately the same as the impurity concentration of said second impurity region portion.

Claim 21

A semiconductor memory device including a memory cell having a selection transistor and a data storage transistor, comprising: a semiconductor substrate of a first conductivity type; a field insulating film formed on said semiconductor substrate to define an element region; first, second, and third impurity regions of a second conductivity type formed in said element region of said semiconductor substrate; a gate electrode of said selection transistor provided above a first channel region between said first and second impurity regions; a floating gate electrode of said data storage transistor having a first electrode portion provided at least partly over a first portion of said second impurity region having a first impurity concentration and a second electrode portion provided over a second channel region between a second portion of said second impurity region having a second impurity concentration and said third impurity region.

Claim 22

A semiconductor memory device including a memory cell having a selection transistor and a data storage transistor, comprising: a semiconductor substrate of a first conductivity type; a field insulating film formed on said semiconductor substrate to define an element region; first, second, and third impurity regions of a second conductivity type formed in said element region of said semiconductor substrate; a gate electrode of said selection transistor provided above a first channel region between said first and second impurity regions; a floating gate electrode of said data storage transistor having a first electrode portion provided at least partly over a first portion of said second impurity region having a first impurity concentration and a second electrode portion provided over a second channel region between a second portion of said second impurity region having a second impurity concentration and said third impurity region.

Claim 23

The semiconductor memory device according to claim 19, wherein said second impurity region includes a third portion having a third impurity concentration such that said first portion of said second impurity region is disposed between said second and third portions of said second impurity region.

Claim 24

The semiconductor memory device according to claim 20, wherein the second and third impurity concentrations are approximately equal.

Claim 25

The semiconductor memory device according to claim 21, wherein the first impurity concentration is greater than the second and third impurity concentrations.

Claim 26

The semiconductor memory device according to claim 19, wherein said second impurity region constitutes a drain of said data storage transistor and a source of said selection transistor.