Patent US5594884A successfully refreshed from Google Patents.
US5594884A
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Cache memory system having a plurality of ports
Assignee: Toshiba Corp
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Filing: 1993-12-21
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Granted: 1997-01-14
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Expires: 2013-12-21
Abstract
Abstract An instruction cache and a data cache are formed with a 2-port structure, the first port of the instruction cache is exclusively used for readout of the contiguous instruction, and the second port thereof is exclusively used for readout of the branched instruction when the conditional branch instruction is executed. With this construction, two instructions which may be executed can be simultaneously fetched irrespective of whether the branch of the conditional branch instruction is taken or untaken, thereby making it possible to enhance the CPU performance. Further, in the 2-port data cache, time for the cache refill process can be reduced by means of the contiguous data transfer and non-cacheable access.
Inventors
- 👤 Tsukasa Matoba
- 👤 Hiroyuki Satou
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 00:25
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3802; G06F9/3804; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0844; G06F12/0853; G06F12/0855; G06F12/0859
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
219 words
A cache memory system for storing part of a group of instructions executed by a CPU, comprising: a plural-port type instruction cache memory having a first instruction readout port for sequentially reading out instructions which are successive in an address order to said CPU and a second instruction readout port for reading out a branched instruction designated by a branch address of a conditional branch instruction to said CPU; an instruction fetch unit for accessing said instruction cache memory wherein an instruction succeeding said conditional branch instruction in an address order and the branched instruction of said conditional branch instruction are simultaneously read out from said instruction cache memory via said first and second instruction readout ports when said conditional branch instruction is fetched to said CPU; a first hit detection circuit for detecting the presence in said instruction cache memory of the instruction succeeding said conditional branch instruction in an address order; a second hit detection circuit for detecting the presence in said instruction cache memory of the branched instruction of said conditional branch instruction; and a memory bus control circuit for preferentially refilling said instruction cache memory for said branched instruction when said first and second hit detection circuits have detected that neither said succeeding instruction nor said branched instruction is present in said instruction cache memory.
Claim 2
Dependent Claim
219 words
A cache memory system for storing part of a group of instructions executed by a CPU, comprising: a plural-port type instruction cache memory having a first instruction readout port for sequentially reading out instructions which are successive in an address order to said CPU and a second instruction readout port for reading out a branched instruction designated by a branch address of a conditional branch instruction to said CPU; an instruction fetch unit for accessing said instruction cache memory wherein an instruction succeeding said conditional branch instruction in an address order and the branched instruction of said conditional branch instruction are simultaneously read out from said instruction cache memory via said first and second instruction readout ports when said conditional branch instruction is fetched to said CPU; a first hit detection circuit for detecting the presence in said instruction cache memory of the instruction succeeding said conditional branch instruction in an address order; a second hit detection circuit for detecting the presence in said instruction cache memory of the branched instruction of said conditional branch instruction; and a memory bus control circuit for preferentially refilling said instruction cache memory for said branched instruction when said first and second hit detection circuits have detected that neither said succeeding instruction nor said branched instruction is present in said instruction cache memory.
Claim 3
Independent Claim
184 words
A method of controlling a cache memory system having a plural-port type instruction cache memory, comprising the steps of: a) sequentially reading out instructions which are successive in address order via a first instruction readout port of said instruction cache memory and reading out a branched instruction designated by a branch address of a conditional branch instruction via a second instruction readout port of said instruction cache memory; b) accessing said instruction cache memory wherein an instruction succeeding said conditional branch instruction in an address order and a branched instruction of said conditional branch instruction are simultaneously read out from said instruction cache memory via said first and second instruction readout ports, respectively, when a conditional branch instruction is fetched; ac) detecting the presence in said instruction cache memory of the instruction succeeding said conditional branch instruction in an address order and the branched instruction of said conditional branch instruction; and d) preferentially refilling said instruction cache memory for said branched instruction when the step c) has detected that neither said succeeding instruction nor said branched instruction is present in said instruction cache memory.
Claim 4
Independent Claim
184 words
A method of controlling a cache memory system having a plural-port type instruction cache memory, comprising the steps of: a) sequentially reading out instructions which are successive in address order via a first instruction readout port of said instruction cache memory and reading out a branched instruction designated by a branch address of a conditional branch instruction via a second instruction readout port of said instruction cache memory; b) accessing said instruction cache memory wherein an instruction succeeding said conditional branch instruction in an address order and a branched instruction of said conditional branch instruction are simultaneously read out from said instruction cache memory via said first and second instruction readout ports, respectively, when a conditional branch instruction is fetched; ac) detecting the presence in said instruction cache memory of the instruction succeeding said conditional branch instruction in an address order and the branched instruction of said conditional branch instruction; and d) preferentially refilling said instruction cache memory for said branched instruction when the step c) has detected that neither said succeeding instruction nor said branched instruction is present in said instruction cache memory.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-01-14 | 2000-07-15 | 2001-01-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-01-14 | 2004-07-15 | 2005-01-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-01-14 | 2008-07-15 | 2009-01-14 | $7700.00 | Window Closed / Lapsed |