US5287465A
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Parallel processing apparatus and method capable of switching parallel and successive processing modes
Assignee: Hitachi Ltd
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Filing: 1990-07-09
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Granted: 1994-02-15
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Expires: 2010-07-09
Abstract
Abstract When executing successive processing of conventional software, a parallel processing apparatus turns a processing state discrimination flag off, increases a program count by 1 at a time, reads out one instruction, and processes that instruction in an arithmetic unit. When executing parallel processing for new software, the parallel processing apparatus turns the processing state discrimination on, increases the program count by m at a time, reads out m instructions, and exercises parallel processing over m instructions in m arithmetic units. In order to select either of the above described two kinds of processing, a discrimination changeover instruction having function of changing over the processing state discrimination flag is added. Instructions are processed in arithmetic unit(s) in accordance with the processing state discrimination flag. In this way, successive processing and parallel processing are provided with compatibility and are selectively executed. Further, the parallel processing apparatus making great account of compatibility of a great part of software reads out m instructions without using the processing state flag, decodes the m instructions, checks whether a branch instruction exists in the k-th instruction, then executes the first to the (k+1)-th instructions in k+1 arithmetic units, and prevent execution of the (k+ 2)-th to m-th instructions. By executing the k-th branch instruction, the parallel processing apparatus calculates an address nm+h of its branch destination, performs calculation to check whether the condition is satisfied or not, then prevents execution of instructions of addresses nm to nm+h-1, and executes instructions of addresses nm+h to (n+1)m. In this way, the parallel processing apparatus executes a plurality of instructions and successively executes branch instructions.
Inventors
- 👤 Kenichi Kurosawa
- 👤 Shigeya Tanaka
- 👤 Yasuhiro Nakatsuka
- 👤 Tadaaki Bandoh
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 08:47
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3885; G06F9/3889; G06F9/30181; G06F9/30189; G06F9/3802; G06F9/3824; G06F9/3836; G06F9/3842; G06F9/3861; G06F9/3867
Claims Analysis
Total Claims: 29
Claim 1
Independent Claim
205 words
A parallel processing apparatus comprising: a program counter for indicating instructions to be read out from a memory; m instruction registers for respectively storing m instructions therein indicated by said program counter; a register file for storing data therein; m arithmetic units sharing said register file and executing arithmetic operations; means for controlling said m arithmetic units to effect either parallel processing of m consecutive instructions read out from an address of the memory indicated by said program counter in said m arithmetic units, or successive processing of consecutive instructions, read out from an address of the memory indicated by said program counter, in one of said m arithmetic units, in response to a processing state alteration instruction; conditional branch instruction processing means responsive to satisfaction of a condition of a conditional branch instruction included in m instructions read out by said program counter for preventing execution of instructions located after an address of an instruction to be executed and included in said m instructions; and unconditional branch instruction processing means responsive to an unconditional branch instruction included in m instructions read out by said program counter for preventing execution of instructions located after an instruction to be executed and included in said m instructions.
Claim 2
Dependent Claim
205 words
A parallel processing apparatus comprising: a program counter for indicating instructions to be read out from a memory; m instruction registers for respectively storing m instructions therein indicated by said program counter; a register file for storing data therein; m arithmetic units sharing said register file and executing arithmetic operations; means for controlling said m arithmetic units to effect either parallel processing of m consecutive instructions read out from an address of the memory indicated by said program counter in said m arithmetic units, or successive processing of consecutive instructions, read out from an address of the memory indicated by said program counter, in one of said m arithmetic units, in response to a processing state alteration instruction; conditional branch instruction processing means responsive to satisfaction of a condition of a conditional branch instruction included in m instructions read out by said program counter for preventing execution of instructions located after an address of an instruction to be executed and included in said m instructions; and unconditional branch instruction processing means responsive to an unconditional branch instruction included in m instructions read out by said program counter for preventing execution of instructions located after an instruction to be executed and included in said m instructions.
Claim 3
Dependent Claim
40 words
A parallel processing apparatus according to claim 1, wherein said conditional branch instruction processing means and said unconditional branch instruction processing means operate to invalidate contents of instruction registers by using a control signal when a branch instruction is decoded.
Claim 4
Dependent Claim
143 words
A parallel processing apparatus according to claim 1, wherein: said conditional branch instruction processing means includes means responsive to a conditional branch instruction existing as a k-th instruction (where k=1, 2, --, m-1) included in m instructions read out by said program counter for executing at least the k-th instruction and a (k+1)-th instruction irrespective of satisfaction or nonsatisfaction of a condition and responsive to satisfaction of the condition for preventing execution of a (k=2)-th instruction and succeeding instructions and for causing branching; and said unconditional branch instruction processing means includes means responsive to said unconditional branch instruction existing as a k-th instruction (where k=1, 2, --, m-1) included in m instructions read out by said program counter for executing at least the k-th instruction and a (k+1)-th instruction, and for preventing execution of a (k+2)-th instruction and succeeding instructions to cause branching.
Claim 5
Dependent Claim
154 words
A parallel processing apparatus according to claim 1, wherein: said conditional branch instruction processing means includes means responsive to a conditional branch instruction existing in an m-th instruction included in m instructions read out by said program counter for executing a first instruction included in m instructions succeeding said m instructions including said conditional branch instruction irrespective of satisfaction or nonsatisfaction of a condition, and responsive to satisfaction of the condition for preventing execution of a second instruction and all instructions succeeding the second instruction and causing branching; and said unconditional branch instruction processing means includes means responsive to an unconditional branch instruction existing in an m-th instruction included in m instructions read out by said program counter for executing a first instruction included in m instructions succeeding said m instructions including said conditional branch instruction and for preventing execution of a second instruction and all instructions succeeding the second instruction and causing branching.
Claim 6
Dependent Claim
210 words
A parallel processing apparatus according to claim 1, wherein: said conditional branch instruction processing means includes means responsive to a conditional branch instruction for branching to an address nm+h and existing as a k-th instruction (where k=1, 2, --, m-1) included in m instructions read out by said program counter for executing at least the k-th instruction and a (k+1)-th instruction irrespective of satisfaction or nonsatisfaction of a condition, and responsive to satisfaction of the condition for preventing execution of a (k+2)-th instruction and succeeding instructions, branching to the address nm+h, preventing execution of instructions of addresses nm to nm+h-1, and effecting execution of instructions of addresses nm+h to (n+1)m in said arithmetic units respectively corresponding thereto; and said unconditional branch instruction processing means includes means responsive to an unconditional branch instruction for branching to an address nm+h and existing as a k-th instruction (where k=1, 2, --, m-1) included in m instructions read out by said program counter for executing at least the k-th instruction and a (k+1)-th instruction, preventing execution of a (k+2)-th instruction and succeeding instructions, branching to the address nm+h, preventing execution of instructions of addresses nm to nm+h-1), and effecting execution of instructions of addresses nm+h to (n+1)m in said arithmetic units respectively corresponding thereto.
Claim 7
Dependent Claim
224 words
A parallel processing apparatus according to claim 1 wherein: said conditional branch instruction processing means includes means responsive to a conditional branch instruction for branching to an address nm+h and existing as an m-th instruction included in m instructions read out by said program counter for executing a first instruction included in m instructions succeeding said m instructions including said conditional branch instructions irrespective of satisfaction or nonsatisfaction of a condition, and responsive to satisfaction of the condition for preventing execution of a second instruction and all instructions succeeding the second instruction, branching to the address nm+h, preventing execution of instructions of addresses nm to nm+h-1, and effecting execution of instructions of addresses nm+h to (n+1) m in said arithmetic units respectively corresponding thereto; and said unconditional branch instruction processing means includes means responsive to an unconditional branch instruction for branching to an address nm+h and existing as an m-th instruction included in m instructions read out by said program counter for executing a first instruction included in m instructions succeeding said m instructions including said conditional branch instruction, preventing execution of a second instruction and all instructions succeeding the second instruction, branching to the address nm+h, preventing execution of instructions of addresses nm to nm+h-1, and effecting execution of instructions of addresses nm+h to (n+1) m in said arithmetic units respectively corresponding thereto.
Claim 8
Dependent Claim
118 words
A parallel processing apparatus according to claim 1, wherein: said conditional branch instruction processing means includes means responsive to a conditional branch instruction existing in a predetermined address and included in m instructions read out by said program counter for executing said m instructions and m instructions of an address succeeding that of said m instructions and causing branching irrespective of satisfaction or nonsatisfaction of a condition; and said unconditional branch instruction processing means includes means responsive to an unconditional branch instruction existing in a predetermined address and included in m instructions read out by said program counter for executing said m instructions and m instructions of an address succeeding that of said m instructions and causing branching.
Claim 9
Dependent Claim
202 words
A parallel processing apparatus comprising: a program counter for indicating instructions to be read out of memory; m instruction registers for storing read-out instructions therein; a register file for storing data therein; m arithmetic units sharing said register file and executing arithmetic operations; means for executing parallel processing of m consecutive instructions read out from an address indicated by said program counter in said m arithmetic units; conditional branch instruction processing means responsive to satisfaction of a condition of a conditional branch instruction included in m instructions read out of memory by said program counter for preventing execution of instructions located in memory at an address subsequent to an instruction to be executed and included in said m instructions; and unconditional branch instruction processing means responsive to an unconditional branch instruction included in said m instructions read out of memory by said program counter for preventing execution of instructions located in memory subsequent to an instruction to be executed and included in said m instructions; wherein said conditional branch instruction processing means and said unconditional branch instruction processing means operate to invalidate contents of the instruction registers by using a control signal when a branch instruction is decoded by the instruction decoders.
Claim 10
Dependent Claim
202 words
A parallel processing apparatus comprising: a program counter for indicating instructions to be read out of memory; m instruction registers for storing read-out instructions therein; a register file for storing data therein; m arithmetic units sharing said register file and executing arithmetic operations; means for executing parallel processing of m consecutive instructions read out from an address indicated by said program counter in said m arithmetic units; conditional branch instruction processing means responsive to satisfaction of a condition of a conditional branch instruction included in m instructions read out of memory by said program counter for preventing execution of instructions located in memory at an address subsequent to an instruction to be executed and included in said m instructions; and unconditional branch instruction processing means responsive to an unconditional branch instruction included in said m instructions read out of memory by said program counter for preventing execution of instructions located in memory subsequent to an instruction to be executed and included in said m instructions; wherein said conditional branch instruction processing means and said unconditional branch instruction processing means operate to invalidate contents of the instruction registers by using a control signal when a branch instruction is decoded by the instruction decoders.
Claim 11
Dependent Claim
143 words
A parallel processing apparatus according to claim 8, wherein: said conditional branch instruction processing means includes means responsive to a conditional branch instruction existing as a k-th instruction (where k=1, 2, --, m-1) included in m instructions read out by said program counter for executing at least the k-th instruction and a (k+1)-th instruction irrespective of satisfaction or nonsatisfaction of a condition and responsive to satisfaction of the condition for preventing execution of a (k+2)-th instruction and succeeding instructions and for causing branching; and said unconditional branch instruction processing means includes means responsive to said unconditional branch instruction existing as a k-th instruction (where k=1, 2, --, m-1) included in m instructions read out by said program counter for executing at least the k-th instruction and a (k+1)-th instruction, and for prefventing execution of a (k+2)-th instruction and succeeding instructions to cause branching.
Claim 12
Dependent Claim
154 words
A parallel processing apparatus according to claim 8, wherein: said conditional branch instruction processing means includes means responsive to a conditional branch instruction existing in an m-th instruction included in m instructions read out by said program counter for executing a first instruction included in m instructions succeeding said m instructions including said conditional branch instruction irrespective of satisfaction or nonsatisfaction of a condition, and responsive to satisfaction of the condition for preventing execution of a second instruction and all instructions succeeding the second instruction and causing branching; and said unconditional branch instruction processing means includes means responsive to an unconditional branch instruction existing in an m-th instruction included in m instructions read out by said program counter for executing a first instruction included in m instructions succeeding said m instructions including said conditional branch instruction and for preventing execution of a second instruction and all instructions succeeding the second instruction and causing branching.
Claim 13
Dependent Claim
210 words
A parallel processing apparatus according to claim 8, wherein: said conditional branch instruction processing means includes means responsive to a conditional branch instruction for branching to an address nm+h and existing as a k-th instruction (where k=1, 2, --, m-1) included in m instructions read out by said program counter for executing at least the k-th instruction and a (k+1)-th instruction irrespective of satisfaction or nonsatisfaction of a condition, and responsive to satisfaction of the condition for preventing execution of a (k+2)-th instruction and succeeding instructions, branching to the address nm+h, preventing execution of instructions of addresses nm to nm+h-1, and effecting execution of instructions of addresses nm+h to (n+1)m in said arithmetic units respectively corresponding thereto; and said unconditional branch instruction processing means includes means responsive to an unconditional branch instruction for branching to an address nm+h and existing as a k-th instruction (where k=1, 2, --, m-1) included in m instructions read out by said program counter for executing at least the k-th instruction and a (k+1)-th instruction, preventing execution of a (k+2)-th instruction and succeeding instructions, branching to the address nm+h, preventing execution of instructions of addresses nm to nm+h-1, and effecting execution of instructions of addresses nm+h to (n+1)m in said arithmetic units respectively corresponding thereto.
Claim 14
Dependent Claim
223 words
A parallel processing apparatus according to claim 8, wherein: said conditional branch instruction processing means includes means responsive to a conditional branch instruction for branching to an address nm+h and existing as an m-th instruction included in m instructions read out by said program counter for executing a first instruction included in m instructions succeeding said m instructions including said conditional branch instruction irrespective of satisfaction or nonsatisfaction of a condition, and responsive to satisfaction of the condition for preventing execution of a second instruction and all instructions succeeding the second instruction, branching to the address nm+h, preventing execution of instructions of addresses nm to nm+h-1, and effecting execution of instructions of addresses nm+h to (n+1)m in said arithmetic units respectively corresponding thereto; and said unconditional branch instruction processing means includes means responsive to an unconditional branch instruction for branching to an address nm+h and existing as an m-th instruction included in m instructions read out by said program counter for executing a first instruction included in m instructions succeeding said m instructions including said conditional branch instruction, preventing execution of a second instruction and all instructions succeeding the second instruction, branching to the address nm+h, preventing execution of instructions of addresses nm to nm+h-1, and effecting execution of instructions of addresses nm+h to (n+1) m in said arithmetic units respectively corresponding thereto.
Claim 15
Dependent Claim
118 words
A parallel processing apparatus according to claim 8, wherein: said conditional branch instruction processing means includes means responsive to a conditional branch instruction existing in a predetermined address and included in m instructions read out by said program counter for executing said m instructions and m instructions of an address succeeding that of said m instructions and causing branching irrespective of satisfaction or nonsatisfaction of a condition; and said unconditional branch instruction processing means includes means responsive to an unconditional branch instruction existing in a predetermined address and included in m instructions read out by said program counter for executing said m instructions and m instructions of an address succeeding that of said m instructions and causing branching.
Claim 16
Dependent Claim
143 words
A parallel processing apparatus comprising: a program counter for indicating instructions to be read out from a memory; m instruction registers for respectively storing m instructions therein indicated by said program counter; a register file for storing data therein; m arithmetic units sharing said register file and executing arithmetic operations; a processor state register for storing a processing state flag indicating either parallel processing of m consecutive instructions read out from an address of said memory indicated by said program counter in the m arithmetic units, or successive processing of consecutive instructions, read out from an address of the memory indicated by said program counter, in one of said m arithmetic units, in response to a processing state alteration instruction; means for controlling said program counter to increment by either m or 1 according to a value indicated by said processing state flag.
Claim 17
Dependent Claim
143 words
A parallel processing apparatus comprising: a program counter for indicating instructions to be read out from a memory; m instruction registers for respectively storing m instructions therein indicated by said program counter; a register file for storing data therein; m arithmetic units sharing said register file and executing arithmetic operations; a processor state register for storing a processing state flag indicating either parallel processing of m consecutive instructions read out from an address of said memory indicated by said program counter in the m arithmetic units, or successive processing of consecutive instructions, read out from an address of the memory indicated by said program counter, in one of said m arithmetic units, in response to a processing state alteration instruction; means for controlling said program counter to increment by either m or 1 according to a value indicated by said processing state flag.
Claim 18
Dependent Claim
41 words
A parallel processing apparatus according to claim 14, further including means for controlling said arithmetic units to effect execution of plural instructions by parallel processing or individual instructions by successive processing according to said value indicated by said processing state flag.
Claim 19
Dependent Claim
23 words
A parallel processing apparatus according to claim 14, further including a sequencer for controlling said program counter, said sequencer comprising a wired-logic circuit.
Claim 20
Dependent Claim
24 words
A parallel processing apparatus according to claim 14, further including a sequencer for controlling said program counter, said sequencer being implemented by a microprogram.
Claim 21
Dependent Claim
141 words
An LSI for parallel processing, comprising: a program counter for indicating instructions to be read out; m instruction registers for respectively storing m instructions therein indicated by said program counter; a register file for storing data therein; m arithmetic units sharing said register file and executing arithmetic operations; and a processor state register responsive to a processing state alteration instruction for selecting one of a plurality of instructions signals for activating said program counter through a pin of a large scaled integrated circuit, said program counter being activated by either a first signal indicating parallel processing of m instructions, read out from an address indicated by said program counter, in said m arithmetic units, or a second signal indicating successive processing of consecutive instructions, read out from an address indicated by said program counter, in one of said m arithmetic units.
Claim 22
Dependent Claim
141 words
An LSI for parallel processing, comprising: a program counter for indicating instructions to be read out; m instruction registers for respectively storing m instructions therein indicated by said program counter; a register file for storing data therein; m arithmetic units sharing said register file and executing arithmetic operations; and a processor state register responsive to a processing state alteration instruction for selecting one of a plurality of instructions signals for activating said program counter through a pin of a large scaled integrated circuit, said program counter being activated by either a first signal indicating parallel processing of m instructions, read out from an address indicated by said program counter, in said m arithmetic units, or a second signal indicating successive processing of consecutive instructions, read out from an address indicated by said program counter, in one of said m arithmetic units.
Claim 23
Dependent Claim
33 words
An LSI for parallel processing, according to claim 18, wherein said processor state register stores a processing state flag for indicating either m or 1 as an increment value of said program counter.
Claim 24
Dependent Claim
118 words
A parallel processing apparatus comprising: a program counter for indicating instructions to be read out from a memory; m instruction registers for respectively storing m instructions therein indicated by said program counter; a register file for storing data therein; m arithmetic units sharing said register file and executing arithmetic operations; means for controlling said m arithmetic units to effect either parallel processing of m consecutive instructions read out from an address of the memory indicated by said program counter in said m arithmetic units, or successive processing of consecutive instructions, read out from an address of the memory indicated by said program counter, in one of said m arithmetic units, in response to a processing state alteration instruction.
Claim 25
Dependent Claim
118 words
A parallel processing apparatus comprising: a program counter for indicating instructions to be read out from a memory; m instruction registers for respectively storing m instructions therein indicated by said program counter; a register file for storing data therein; m arithmetic units sharing said register file and executing arithmetic operations; means for controlling said m arithmetic units to effect either parallel processing of m consecutive instructions read out from an address of the memory indicated by said program counter in said m arithmetic units, or successive processing of consecutive instructions, read out from an address of the memory indicated by said program counter, in one of said m arithmetic units, in response to a processing state alteration instruction.
Claim 26
Dependent Claim
111 words
An parallel processing method comprising the steps of: indicating instructions to be read out of memory by using a program counter; storing read-out instructions into m instruction registers; storing data into a register file; and when conducting the arithmetic operation in m arithmetic units sharing said register file, controlling execution means to selectively execute either parallel processing of m consecutive instructions read out from an address in memory indicated by said program counter in said m arithmetic units, or successive processing of consecutive instructions read out from an address in memory indicated by said program counter in one of said m arithmetic units, in response to a processing state alteration instruction.
Claim 27
Dependent Claim
111 words
An parallel processing method comprising the steps of: indicating instructions to be read out of memory by using a program counter; storing read-out instructions into m instruction registers; storing data into a register file; and when conducting the arithmetic operation in m arithmetic units sharing said register file, controlling execution means to selectively execute either parallel processing of m consecutive instructions read out from an address in memory indicated by said program counter in said m arithmetic units, or successive processing of consecutive instructions read out from an address in memory indicated by said program counter in one of said m arithmetic units, in response to a processing state alteration instruction.
Claim 28
Dependent Claim
160 words
A parallel processing method comprising the steps of: indicating instructions to be read out of memory by using a program counter; storing read-out instructions into m instruction registers; storing data into a register file; when conducting an arithmetic operation in m arithmetic units sharing said register file, storing a processing state flag indicating processing state either parallel processing of m consecutive instructions read out from an address in memory indicated by said program counter in the m arithmetic units, or successive processing of consecutive instructions read out from an address in memory indicated by said program counter in one of said arithmetic units, in response to a processing state alteration instruction; controlling said program counter to increment by either m or 1 according to a value indicated by said processing state flag; and controlling said arithmetic units to execute plural instructions by parallel processing or individual instructions by successive processing according to said value indicated by said processing state flag.
Claim 29
Dependent Claim
160 words
A parallel processing method comprising the steps of: indicating instructions to be read out of memory by using a program counter; storing read-out instructions into m instruction registers; storing data into a register file; when conducting an arithmetic operation in m arithmetic units sharing said register file, storing a processing state flag indicating processing state either parallel processing of m consecutive instructions read out from an address in memory indicated by said program counter in the m arithmetic units, or successive processing of consecutive instructions read out from an address in memory indicated by said program counter in one of said arithmetic units, in response to a processing state alteration instruction; controlling said program counter to increment by either m or 1 according to a value indicated by said processing state flag; and controlling said arithmetic units to execute plural instructions by parallel processing or individual instructions by successive processing according to said value indicated by said processing state flag.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-02-14 | 1997-08-16 | 1998-02-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-02-14 | 2001-08-16 | 2002-02-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-02-14 | 2005-08-16 | 2006-02-15 | $7700.00 | Window Closed / Lapsed |