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EP0147858A2 Expired / Lapsed EP ⏱️ 0.0 years remaining

Vector processing apparatus

Assignee: Hitachi Ltd
•
Filing: 1984-12-27
•
Granted: —
•
Expires: 2004-12-27
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Abstract

Abstract A vector processing apparatus has a number of pipeline arithmetic units (30-33) operating concurrently to execute a set of vector instructions dealing with vector elements. Stack registers (301-309) are provided for each arithmetic unit to hold the vector instruction address, leading vector element position and vector register internal address, so that one of exceptions that can be detected successively by several arithmetic units during the process of the vector instructions is selected on a priority basis through the comparison of information in the stack of the currently detected exception with information of exception detected previously.

Inventors

  • 👤 Yaoko Yoshida

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-10-31 17:29
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3861; G06F9/3865; G06F15/00; G06F15/76; G06F15/80; G06F15/8053; G06F15/8076

Claims Analysis

Total Claims: 5
Claim 1
Independent Claim 111 words
A vector processing apparatus having a plurality of functional facilities (30-33) capable of operating concurrently and intended to process vectors with elements more in number than those which a vector register (10-17) can store, said apparatus comprising means (306-309, 302-305, 301) for holding in correspondence to said functional facilities the address of an instruction under process by a functional facility, leading vector element position processed by said instruction and vector register internal address of a vector element at which exception has been detected by said functional facility, and means (8) for reading out information in said holding means in response to a report of detection of exception from each functional facility.
Claim 2
Dependent Claim 111 words
A vector processing apparatus having a plurality of functional facilities (30-33) capable of operating concurrently and intended to process vectors with elements more in number than those which a vector register (10-17) can store, said apparatus comprising means (306-309, 302-305, 301) for holding in correspondence to said functional facilities the address of an instruction under process by a functional facility, leading vector element position processed by said instruction and vector register internal address of a vector element at which exception has been detected by said functional facility, and means (8) for reading out information in said holding means in response to a report of detection of exception from each functional facility.
Claim 3
Dependent Claim 16 words
A vector processing apparatus according to claim 1, wherein said functional facilities comprise pipeline arithmetic units.
Claim 4
Dependent Claim 35 words
A vector processing apparatus according to claim 2, wherein said holding means comprises means for holding the address of instruction and leading vector element position in correspondence to arithmetic stages of said pipeline arithmetic unit.
Claim 5
Dependent Claim 23 words
A vector processing apparatus according to claim 3, wherein said exception includes at least one of an access exception and an arithmetic exception.

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