Bus interface structure and system for controlling the bus interface structure

Claim 1

A bus interface structure for a multiprocessor system, the bus interface structure comprising: a bus interface having a first end connected to a system bus and a second end; a local bus connected to said second end of said bus interface; a common memory; and a memory controller for controlling said common memory and being connected at one end thereof to said local bus and at another end thereof to said common memory to transfer data from an MPU of said multiprocessor system to said common memory, said memory controller including a buffer having a capacity for only one block transfer at a time, said memory controller reading out one-word data and block data from said common memory; said bus interface comprising a burst disassembling control circuit for disassembling burst transfer data into one or a plurality of block data transfers and one or a plurality of one-word data transfers, wherein said first transfer data is disassembled to transfer the burst transfer data by using said buffer having a capacity for only one block transfer at a time, said disassembled burst transfer data being supplied to said memory controller, and said burst disassembling control circuit determining whether a block data transfer or a word data transfer is to be selected in accordance with a transmission starting address of said common memory and the number of words to be transferred.