Non-volatile semiconductor memory capable of erase- verifying memory cells in a test mode using a defective count circuit activated by a test mode signal

Claim 1

A non-volatile semiconductor memory including a plurality of memory cells arranged in the form of a matrix, an erase means for simultaneously erasing said plurality of memory cells, a discriminating means for discriminating whether or not each one of said plurality of memory cells has been erased, an internal address generating means for supplying said discriminating means with an internal address for accessing each of said plurality of memory cells, a control means for controlling said erase means and said discriminating means in such a manner that, after a pre-erase writing is performed, said simultaneous erasing of said erasing means and said discrimination of said discriminating means are alternately performed, and a count means for counting the number of memory cells which are discriminated to be unerased by said discriminating means, said count means outputting to said control means an erase failure signal when the counted number becomes higher than a predetermined count limit number, said control means responding to said erase failure signal for stopping an operation of said discriminating means and for causing said erasing means to restart said simultaneous erasing.