Low current reduced area programming voltage detector for flash memory

Claim 2

A voltage detector circuit for detecting whether a first supply voltage exceeds a predetermined voltage as the first supply voltage ramps towards its final value comprising: a first transistor having a first terminal coupled to the first supply voltage, a second terminal coupled to a first node, and a control electrode coupled to receive a first voltage that varies as the first supply voltage ramps towards its final value, the first transistor being operative to set the first node to a logic high level in response to the first voltage when the first supply voltage exceeds the predetermined voltage; and a second transistor having a first terminal coupled to the first node, a second terminal coupled to system ground, and a control electrode coupled to receive a second voltage that varies as the first supply voltage ramps towards its final value, the second transistor being operative to set the first node to a logic low level when the first supply voltage is less than the predetermined voltage, wherein the first and second voltages are such that a difference in potential between the control electrode of the first transistor and the first terminal of the first transistor is always approximately equal to a difference in potential between the control electrode of the second transistor and the second terminal of the second transistor.

Claim 3

The voltage detector circuit of claim 1, further comprising: a voltage divider circuit including a plurality of resistive devices coupled in series between the first supply voltage and system ground, wherein each of the first and second voltages is received from a different node between resistive devices.

Claim 4

A voltage detector circuit for determining when a first supply voltage exceeds a predetermined voltage as the first supply voltage ramps towards its final value, comprising: a plurality of resistive devices coupled in series between the first supply voltage and system ground; a first transistor coupled to the first supply voltage and an output node, the first transistor receiving a first biasing voltage that varies as the first supply voltage ramps towards its final value from a first node defined between a first pair of resistive devices, the first transistor being operative to set the output node to a logic high level when the first supply voltage exceeds the predetermined voltage; a second transistor coupled to system ground and the output node, the second transistor receiving a second biasing voltage that varies as the first supply voltage ramps towards its final value from a second node defined between a second pair of resistive devices, wherein a difference between the second biasing voltage and system ground is equal to a difference between the first biasing voltage and the first supply voltage, the second transistor being operative to set the output node to a logic low level when the first supply voltage is less than the predetermined voltage; and a third transistor coupled between the second transistor and system ground, the third transistor receiving a third biasing voltage from a third node defined between a third pair of resistive devices.

Claim 5

A voltage detector circuit for determining when a first supply voltage exceeds a predetermined voltage as the first supply voltage ramps towards its final value, comprising: a plurality of resistive devices coupled in series between the first supply voltage and system ground; a first transistor coupled to the first supply voltage and an output node, the first transistor receiving a first biasing voltage that varies as the first supply voltage ramps towards its final value from a first node defined between a first pair of resistive devices, the first transistor being operative to set the output node to a logic high level when the first supply voltage exceeds the predetermined voltage; a second transistor coupled to system ground and the output node, the second transistor receiving a second biasing voltage that varies as the first supply voltage ramps towards its final value from a second node defined between a second pair of resistive devices, wherein a difference between the second biasing voltage and system ground is equal to a difference between the first biasing voltage and the first supply voltage, the second transistor being operative to set the output node to a logic low level when the first supply voltage is less than the predetermined voltage; and a third transistor coupled between the second transistor and system ground, the third transistor receiving a third biasing voltage from a third node defined between a third pair of resistive devices.

Claim 6

The voltage detector circuit of claim 3 wherein the plurality of resistive devices comprises: a first resistive device coupled between the first supply voltage and the first node; a second resistive device coupled between the first node and the second node; a third resistive device coupled between the second node and the third node; and a fourth resistive device coupled between the third node and system ground.

Claim 7

The voltage detector circuit of claim 4, wherein a resistance value for each of the plurality of resistive devices is equal.

Claim 8

The voltage detector circuit of claim 5, wherein each of the resistive devices is a transistor.

Claim 9

The voltage detector circuit of claim 6, wherein a fourth transistor is coupled in parallel with the first resistive device between the first supply voltage and the first node, the fourth transistor for setting the first node to the first supply voltage when the first supply voltage is approximately equal to a second supply voltage.

Claim 10

The voltage detector circuit of claim 3, further comprising: a fourth transistor coupled to a second supply voltage, the output node, and a fourth node, the fourth transistor setting the fourth node to the second supply voltage in response to the output node being at a logic low level; and a fifth transistor coupled to system ground, the output node, and the fourth node, the fifth transistor setting the fourth node to system ground when the output node is at a logic high level; and a sixth transistor coupled to the first supply voltage, the second supply voltage, and the fourth node, the sixth transistor for setting the fourth node to the second supply voltage when the second supply voltage exceeds the first supply voltage by at least a threshold voltage of the sixth transistor.

Claim 11

The voltage detector circuit of claim 3, wherein the first transistor is a p-channel field effect transistor and the third transistor is an n-channel field effect transistor, the predetermined voltage being set by threshold voltages and beta values of the first and third transistors.

Claim 12

A nonvolatile memory device comprising: an array of memory cells; a first input for receiving a first supply voltage for programming the array of memory cells, wherein the first supply voltage is selectively coupled to the array of memory cells; a second input for receiving a second supply voltage for operating circuitry of the nonvolatile memory device, wherein the second supply voltage is selectively coupled to the array of memory cells; a voltage detector circuit coupled to the first and second inputs for determining when the first supply voltage exceeds a predetermined voltage as the first supply voltage ramps towards its final value, the voltage detector circuit comprising: a plurality of resistive devices coupled in series between the first supply voltage and system ground; a first transistor coupled to the first supply voltage and an output node, the first transistor receiving a first biasing voltage that varies as the first supply voltage ramps towards its final value from a first node defined between a first pair of resistive devices, the first transistor being operative to set the output node to a logic high level when the first supply voltage exceeds the predetermined voltage; a second transistor coupled to system ground and the output node, the second transistor receiving a second biasing voltage that varies as the first supply voltage ramps towards its final value from a second node defined between a second pair of resistive devices, wherein a difference between the second biasing voltage and system ground is equal to a difference between the first biasing voltage and the first supply voltage, the second transistor being operative to set the output node to a logic low level when the first supply voltage is less than the predetermined voltage; and a third transistor coupled between the second transistor and system ground, the third transistor receiving a third biasing voltage from a third node defined between a third pair of resistive devices.

Claim 13

A nonvolatile memory device comprising: an array of memory cells; a first input for receiving a first supply voltage for programming the array of memory cells, wherein the first supply voltage is selectively coupled to the array of memory cells; a second input for receiving a second supply voltage for operating circuitry of the nonvolatile memory device, wherein the second supply voltage is selectively coupled to the array of memory cells; a voltage detector circuit coupled to the first and second inputs for determining when the first supply voltage exceeds a predetermined voltage as the first supply voltage ramps towards its final value, the voltage detector circuit comprising: a plurality of resistive devices coupled in series between the first supply voltage and system ground; a first transistor coupled to the first supply voltage and an output node, the first transistor receiving a first biasing voltage that varies as the first supply voltage ramps towards its final value from a first node defined between a first pair of resistive devices, the first transistor being operative to set the output node to a logic high level when the first supply voltage exceeds the predetermined voltage; a second transistor coupled to system ground and the output node, the second transistor receiving a second biasing voltage that varies as the first supply voltage ramps towards its final value from a second node defined between a second pair of resistive devices, wherein a difference between the second biasing voltage and system ground is equal to a difference between the first biasing voltage and the first supply voltage, the second transistor being operative to set the output node to a logic low level when the first supply voltage is less than the predetermined voltage; and a third transistor coupled between the second transistor and system ground, the third transistor receiving a third biasing voltage from a third node defined between a third pair of resistive devices.

Claim 14

The nonvolatile memory device of claim 10 wherein the plurality of resistive devices comprises: a first resistive device coupled between the first supply voltage and the first node; a second resistive device coupled between the first node and the second node; a third resistive device coupled between the second node and the third node; and a fourth resistive device coupled between the third node and system ground.

Claim 15

The nonvolatile memory device of claim 11, wherein a resistance value for each of the plurality of resistive devices is equal.

Claim 16

The nonvolatile memory device of claim 12, wherein each of the resistive devices is a transistor.

Claim 17

The nonvolatile memory device of claim 13, wherein a fourth transistor is coupled in parallel with the first resistive device between the first supply voltage and the first node, the fourth transistor for setting the first node to the first supply voltage when the first supply voltage is approximately equal to a second supply voltage.

Claim 18

The nonvolatile memory device of claim 10, the voltage detector circuit further comprising: a fourth transistor coupled to a second supply voltage, the output node, and a fourth node, the fourth transistor setting the fourth node to the second supply voltage in response to the output node being at a logic low level; and a fifth transistor coupled to system ground, the output node, and the fourth node, the fifth transistor setting the fourth node to system ground when the output node is at a logic high level; and a sixth transistor coupled to the first supply voltage, the second supply voltage, and the fourth node, the sixth transistor for setting the fourth node to the second supply voltage when the second supply voltage exceeds the first supply voltage by at least a threshold voltage of the sixth transistor.

Claim 19

The nonvolatile memory device of claim 10, wherein the first transistor is a p-channel field effect transistor and the third transistor is an n-channel field effect transistor, the predetermined voltage being set by threshold voltages and beta values of the first and third transistors.

Claim 20

A voltage detector circuit for detecting whether a supply voltage exceeds a predetermined voltage comprising: a plurality of resistive devices coupled to define a first node, a second node, and a third node between the supply voltage and system ground; a first transistor having a gate coupled to the first node, a source coupled to the supply voltage, and a drain coupled to a first output node; a second transistor having a gate coupled to the second node, a source coupled to the first output node, and a drain; a third transistor having a gate coupled to the third node, a source coupled to system ground, and a drain coupled the drain of the second transistor; a fourth transistor having a gate coupled to the first output node, a source coupled to a second supply voltage, and a drain coupled to a second output node; a fifth transistor having a gate coupled to the first output node, a source, and a drain coupled to the second output node; a sixth transistor having a gate coupled to the third node, a drain coupled to the source of the fifth transistor, and a source; a seventh transistor having a gate coupled to the supply voltage, a source coupled to system ground, and a drain coupled to the source of the sixth transistor; and an eighth transistor having a gate coupled to the supply voltage, a source coupled to the second supply voltage, and a drain coupled to the second output node.

Claim 21

A voltage detector circuit for detecting whether a supply voltage exceeds a predetermined voltage comprising: a plurality of resistive devices coupled to define a first node, a second node, and a third node between the supply voltage and system ground; a first transistor having a gate coupled to the first node, a source coupled to the supply voltage, and a drain coupled to a first output node; a second transistor having a gate coupled to the second node, a source coupled to the first output node, and a drain; a third transistor having a gate coupled to the third node, a source coupled to system ground, and a drain coupled the drain of the second transistor; a fourth transistor having a gate coupled to the first output node, a source coupled to a second supply voltage, and a drain coupled to a second output node; a fifth transistor having a gate coupled to the first output node, a source, and a drain coupled to the second output node; a sixth transistor having a gate coupled to the third node, a drain coupled to the source of the fifth transistor, and a source; a seventh transistor having a gate coupled to the supply voltage, a source coupled to system ground, and a drain coupled to the source of the sixth transistor; and an eighth transistor having a gate coupled to the supply voltage, a source coupled to the second supply voltage, and a drain coupled to the second output node.