LDD semiconductor device with peak impurity concentrations

Claim 2

A semiconductor device comprising: (a) a semiconductor substrate including a first conductivity type impurity, said substrate having a first peak concentration of said first conductivity type impurity located along a depth direction of said semiconductor substrate; (b) source and drain regions of a second conductivity type impurity selectively formed in an upper portion of said semiconductor substrate and including a concentration of said first conductivity type impurity, said source and drain regions making a pair to form an LDD construction said drain region having a second peak concentration of said first conductivity type impurity located along a depth direction of said drain region and said substrate; and (c) a buried layer formed in said upper portion of said semiconductor substrate between said source and drain regions, wherein a valley concentration of said first conductivity type impurity is located between said first peak concentration and said second peak concentration of the first conductivity type impurity.

Claim 3

A semiconductor device comprising: (a) a semiconductor substrate having an upper surface; and (b) a first MOS transistor including: (b-1) source and drain regions including a concentration of a first conductivity type impurity and a lesser concentration of a second conductivity type impurity selectively formed in said upper surface of said semiconductor substrate and making a pair to form an LDD construction said drain region having a bottom; (b-2) a first punch-through stopper layer including a concentration of a second conductivity type impurity formed in said upper surface of said semiconductor substrate between said source and drain regions, a peak of the concentration of the second conductivity type impurity of said first punch-through stopper layer being closer to said upper surface of said semiconductor substrate than the bottom of said drain region wherein said bottom of said drain region is located at a depth along a depth direction of said drain region where the concentration of the first conductivity type impurity equals the concentration of the second conductivity type impurity; (b-3) a buried layer formed in an upper portion of said first punch-through stopper layer; (b-4) a gate oxide film formed on said buried layer; and (b-5) a gate electrode opposed to said buried layer, with said gate oxide film therebetween.

Claim 4

A semiconductor device comprising: (a) a semiconductor substrate having an upper surface; and (b) a first MOS transistor including: (b-1) source and drain regions including a concentration of a first conductivity type impurity and a lesser concentration of a second conductivity type impurity selectively formed in said upper surface of said semiconductor substrate and making a pair to form an LDD construction said drain region having a bottom; (b-2) a first punch-through stopper layer including a concentration of a second conductivity type impurity formed in said upper surface of said semiconductor substrate between said source and drain regions, a peak of the concentration of the second conductivity type impurity of said first punch-through stopper layer being closer to said upper surface of said semiconductor substrate than the bottom of said drain region wherein said bottom of said drain region is located at a depth along a depth direction of said drain region where the concentration of the first conductivity type impurity equals the concentration of the second conductivity type impurity; (b-3) a buried layer formed in an upper portion of said first punch-through stopper layer; (b-4) a gate oxide film formed on said buried layer; and (b-5) a gate electrode opposed to said buried layer, with said gate oxide film therebetween.

Claim 5

The semiconductor device of claim 2, wherein said first MOS transistor further includes (b-6) a second punch-through stopper layer disposed under said bottom of said drain region and said first punch-through stopper layer, and being of the same conductivity type as said first punch-through stopper layer and having an impurity concentration lower than that of said first punch-through stopper layer.

Claim 6

The semiconductor device of claim 2, further comprising (c) a surface channel type second MOS transistor of the same conductivity type as said first MOS transistor and formed on said semiconductor substrate.

Claim 7

The semiconductor device of claim 2, further comprising: (c) a second MOS transistor of opposite conductivity type to said first MOS transistor, said second MOS transistor including: (c-1) source and drain regions selectively formed in said upper surface of said semiconductor substrate and making a pair to form to an LDD construction; (c-2) a punch-through stopper layer formed in said upper surface of said semiconductor substrate between said source and drain regions of said second MOS transistor, a peak of a concentration of a first conductivity type impurity concentration of said punch-through stopper layer of said second MOS transistor being closer to said upper surface of said semiconductor substrate than the bottom of said drain region of said second MOS transistor said bottom of said drain region is located at a depth along a depth direction of said drain region of said second MOS transistor where the concentration of the first conductivity type impurity equals a concentration of a second conductivity type impurity; (c-3) a buried layer formed in an upper portion of said punch-through stopper layer of said second MOS transistor said buried layer having a peak of a second conductivity type impurity concentration; (c-4) a gate oxide film formed on said buried layer of said second MOS transistor; and (c-5) a gate electrode opposed to said buried layer of said second MOS transistor, with said gate oxide film of said second MOS transistor therebetween, and wherein the peak of the second conductivity type impurity concentration of said buried layer of said second MOS transistor is at the same depth as a peak of the impurity concentration of said first punch-through stopper layer of said first MOS transistor.