Internal power-supply voltage supplier of semiconductor integrated circuit

Claim 2

An internal power-supply voltage supplier comprising: a driver having an external input terminal coupled to an external power supply, a control input terminal and an output terminal, said driver providing to said output terminal an internal power-supply voltage having a desired internal voltage level; an offset generator having an output connected to said control input terminal of said driver, said offset generator receiving a reference voltage and said internal power-supply voltage and outputting to said offset generator output an offset corresponding to a difference in voltage levels between said reference voltage and said internal power-supply voltage, said offset generator using two differentially connected transistors having different channel widths to ensure that said offset is produced when said difference is minimal; and a power-up controller which receives said reference voltage and said internal power-supply voltage and reduces the voltage level of said internal power-supply voltage when said internal power-supply voltage exceeds said reference voltage by a predetermined voltage level.

Claim 3

The internal power-supply voltage supplier as claimed in claim 1, wherein: said two differentially connected transistors of said offset generator are first and second NMOS transistors, said first NMOS transistor being controlled by said reference voltage, said second NMOS transistor being controlled by said internal power-supply voltage, said first NMOS transistor having a channel width greater than that of said second NMOS transistor, and wherein said driver is a transistor.

Claim 4

The internal power-supply voltage supplier as claimed in claim 2, wherein the channel of said first NMOS transistor has a width-length ratio of approximately 20 and the channel of said second NMOS transistor has a width-length ratio of approximately 15.

Claim 5

An internal power-supply voltage supplier of a semiconductor integrated circuit comprising: a driver having an external input terminal coupled to an external power supply voltage, a control input terminal and an output terminal, said driver providing to said output terminal an internal power-supply voltage having a desired internal voltage level; a first level down shifter for receiving a reference voltage and reducing said reference voltage by a first predetermined amount to a first voltage level below said external power-supply voltage; a second level down shifter for receiving said internal power-supply voltage and reducing said internal power-supply voltage by a second predetermined amount to a second voltage level below said external power-supply voltage; an offset generator having input terminals receiving said first and second voltage levels and having an output coupled to said control input terminal of said driver, said offset generator outputting to said offset generator output an offset corresponding to a difference between said first and second voltage levels, said offset generator using two differentially connected transistors having different channel widths to ensure that said offset is produced when said difference is minimal; and a power-up controller which receives said reference voltage and said internal power-supply voltage and reduces the voltage level of said internal power-supply voltage when said internal power-supply voltage exceeds said reference voltage by a predetermined voltage level.

Claim 6

An internal power-supply voltage supplier of a semiconductor integrated circuit comprising: a driver having an external input terminal coupled to an external power supply voltage, a control input terminal and an output terminal, said driver providing to said output terminal an internal power-supply voltage having a desired internal voltage level; a first level down shifter for receiving a reference voltage and reducing said reference voltage by a first predetermined amount to a first voltage level below said external power-supply voltage; a second level down shifter for receiving said internal power-supply voltage and reducing said internal power-supply voltage by a second predetermined amount to a second voltage level below said external power-supply voltage; an offset generator having input terminals receiving said first and second voltage levels and having an output coupled to said control input terminal of said driver, said offset generator outputting to said offset generator output an offset corresponding to a difference between said first and second voltage levels, said offset generator using two differentially connected transistors having different channel widths to ensure that said offset is produced when said difference is minimal; and a power-up controller which receives said reference voltage and said internal power-supply voltage and reduces the voltage level of said internal power-supply voltage when said internal power-supply voltage exceeds said reference voltage by a predetermined voltage level.

Claim 7

The internal power-supply voltage supplier as claimed in claim 4, wherein each of said first and second level down shifters is comprised of a diode.

Claim 8

The internal power-supply voltage supplier as claimed in claim 5, wherein said two differentially connected transistors of said offset generator are first and second NMOS transistors, said first NMOS transistor being controlled by said first voltage level, said second NMOS transistor being controlled by said second voltage level, said first NMOS transistor having a channel width greater than that of said second NMOS transistor.

Claim 9

The internal power-supply voltage supplier as claimed in claim 6, wherein the channel of said first NMOS transistor has a width-length ratio of approximately 20 and the channel of said second NMOS transistor has a width-length ratio of approximately 15.

Claim 10

An internal power-supply voltage supplier of a semiconductor integrated circuit comprising: a driver having an external input terminal coupled to an external power-supply voltage, a control input terminal and an output terminal, said driver providing to said output terminal an internal power-supply voltage having a desired internal voltage level; an offset generator having an output connected to said control input terminal of said driver, said offset generator receiving a reference voltage and said internal power-supply voltage and outputting to said offset generator output an offset corresponding to a difference in voltage levels between said reference voltage and said internal power-supply voltage, said offset generator using first and second differentially connected transistors having different channel widths to ensure that said offset is produced when said difference is minimal; and a power-up controller for receiving said reference voltage and said internal power-supply voltage and reducing the voltage level of said internal power-supply voltage when said internal power-supply voltage exceeds said reference voltage by a predetermined voltage level.

Claim 11

An internal power-supply voltage supplier of a semiconductor integrated circuit comprising: a driver having an external input terminal coupled to an external power-supply voltage, a control input terminal and an output terminal, said driver providing to said output terminal an internal power-supply voltage having a desired internal voltage level; an offset generator having an output connected to said control input terminal of said driver, said offset generator receiving a reference voltage and said internal power-supply voltage and outputting to said offset generator output an offset corresponding to a difference in voltage levels between said reference voltage and said internal power-supply voltage, said offset generator using first and second differentially connected transistors having different channel widths to ensure that said offset is produced when said difference is minimal; and a power-up controller for receiving said reference voltage and said internal power-supply voltage and reducing the voltage level of said internal power-supply voltage when said internal power-supply voltage exceeds said reference voltage by a predetermined voltage level.

Claim 12

The internal power-supply voltage supplier as claimed in claim 8, further comprising: a first level down shifter for receiving said reference voltage and reducing said reference voltage by a first predetermined amount to a first voltage level below said external power-supply voltage and having an output connected to said first differentially connected transistor of said offset generator; and a second level down shifter for receiving said internal power-supply voltage and reducing said internal power-supply voltage by a second predetermined amount to a second voltage level below said external power-supply voltage and having an output connected to said second differentially connected transistor of said offset generator.

Claim 13

The internal power-supply voltage supplier as claimed in claim 9, wherein each of said first and second level down shifters is comprised of a diode.

Claim 14

The internal power-supply voltage supplier as claimed in claim 10, wherein each of said first and second differentially connected transistors is comprised of an NMOS transistor, said first differentially connected transistor having a current driving ability greater than that of said second differentially connected transistor.

Claim 15

The internal power-supply voltage supplier as claimed in claim 11, wherein the channel of said first transistor has a width-length ratio of approximately 20 and the channel of said second transistor has a width-length ratio of approximately 15.

Claim 16

An internal power-supply voltage supplier of a semiconductor integrated circuit which inputs a reference voltage having a voltage level corresponding to a desired voltage level comprising: a first level down shifter for receiving said reference voltage and for reducing said reference voltage by a first predetermined amount to a first voltage level below an external power-supply voltage; a second level down shifter for receiving an internal power-supply voltage and reducing said internal power-supply voltage by a second predetermined amount to a second voltage level below said external power-supply voltage; an offset generator for receiving said first and second voltage levels and generating an offset corresponding to a difference therebetween, said offset generator using two differentially connected transistors having different channel widths to generate said offset when said difference is minimal; an internal power driver for outputting said internal power-supply voltage having an output voltage level substantially at said desired voltage level, said internal power driver being controlled by said offset; and a power-up controller for receiving said reference voltage and said internal power-supply voltage and controlling the voltage level of said reference voltage and the voltage level of said internal power-supply voltage in order to prevent variation of said internal power-supply voltage from occurring upon power-up of a chip.

Claim 17

An internal power-supply voltage supplier of a semiconductor integrated circuit which inputs a reference voltage having a voltage level corresponding to a desired voltage level comprising: a first level down shifter for receiving said reference voltage and for reducing said reference voltage by a first predetermined amount to a first voltage level below an external power-supply voltage; a second level down shifter for receiving an internal power-supply voltage and reducing said internal power-supply voltage by a second predetermined amount to a second voltage level below said external power-supply voltage; an offset generator for receiving said first and second voltage levels and generating an offset corresponding to a difference therebetween, said offset generator using two differentially connected transistors having different channel widths to generate said offset when said difference is minimal; an internal power driver for outputting said internal power-supply voltage having an output voltage level substantially at said desired voltage level, said internal power driver being controlled by said offset; and a power-up controller for receiving said reference voltage and said internal power-supply voltage and controlling the voltage level of said reference voltage and the voltage level of said internal power-supply voltage in order to prevent variation of said internal power-supply voltage from occurring upon power-up of a chip.

Claim 18

The internal power-supply voltage supplier as claimed in claim 13, wherein each of said first and second level down shifters is comprised of a diode.

Claim 19

The internal power-supply voltage supplier as claimed in claim 14, wherein said two differentially connected transistors of said offset generator are first and second NMOS transistors, said first NMOS transistor being controlled by said first voltage level, said second NMOS transistor being controlled by said second voltage level, said first NMOS transistor having a channel width greater than that of said second-NMOS transistor.

Claim 20

The internal power-supply voltage supplier as claimed in claim 14, wherein said power-up controller comprises: a first PMOS transistor for receiving said reference voltage at a source thereof and having a gate and a drain coupled commonly to each other; a first NMOS transistor having a first channel formed between the drain of said first PMOS transistor and a ground potential, and switching-controlled by a second reference voltage; a second PMOS transistor for receiving said internal power-supply voltage at a source thereof and having a gate coupled commonly to the gate of said first PMOS transistor; a second NMOS transistor having a second channel formed between the drain of said second PMOS transistor and said ground potential, and switching-controlled by said second reference voltage; and a bipolar transistor having a third channel formed between the source of said second PMOS transistor and said ground potential, and switching-controlled by a voltage applied to the drain of said second PMOS transistor.

Claim 21

The internal power-supply voltage supplier as claimed in claim 15, wherein the channel of said first NMOS transistor has a width-length ratio of approximately 20 and the channel of said second NMOS transistor has a width-length ratio of approximately 15.