Source voltage control circuit

Claim 2

A source voltage control circuit comprising: reference voltage generating means connected to an external source voltage terminal for generating a constant reference voltage; source voltage level sensing means connected to said external source voltage terminal for linearly increasing internal voltage when said external source voltage is equal to or greater than a given voltage; first deferential amplifying means with two inputs receiving respectively the outputs of said reference voltage generating means and of said internal source voltage controlled by a first control signal and the output of said source voltage level sensing means; and second differential amplifying means with two inputs receiving the outputs of said reference voltage generating means and said internal source voltage controlled by a second control signal.

Claim 3

A source voltage circuit control circuit as claimed in claim 1, wherein said reference voltage generating means comprises: a first NMOS transistor and diode-connected PMOS transistor connected in series between said external source voltage and a control node; a resistor and pull-down PMOS transistor connected in parallel between said control node and ground voltage terminal; an output node connected to the gate of said first NMOS transistor; and a driving PMOS transistor with the channel connected between said external source voltage terminal and said output node and the gate connected to said control node.

Claim 4

A source voltage control circuit as claimed in claim 2, wherein said reference voltage generating means further comprises a current path means including a plurality of diode-connected PMOS transistors connected between said output node and ground voltage terminal.

Claim 5

A source voltage control circuit as claimed in claim 1, wherein said source voltage level sensing means comprises: voltage drop means connected in series between said external source voltage terminal and a sensing node; a resistor connected between said sensing node and ground voltage terminal; diode-connected NMOS transistors connected in series to said sensing node; a second NMOS transistor with the channel connected between said transistor and ground voltage terminal and the gate connected to said first control signal; a third diode-connected NMOS transistor connected to said sensing node; and a fourth NMOS transistor with the channel connected between the source of said third NMOS transistor and ground voltage terminal and the gate connected to said first control signal.

Claim 6

A source voltage control circuit as claimed in claim 1, wherein said first differential amplifying means comprises: a first singly-ended N-channel input differential amplifier with two inputs receiving the voltage of the output node of said reference voltage generating means and said internal source voltage; a fifth PMOS transistor with the channel connected between said external voltage terminal and the output node of said first differential amplifier and the gate connected to said first control signal; an eight and ninth NMOS transistors with the channels connected in series between said output node and ground voltage terminal and the gates respectively connected to said sensing node and said first control signal; and a sixth PMOS transistor with the channel connected between said external source voltage terminal and said internal source voltage and the gate connected to said output node.

Claim 7

A source voltage control circuit as claimed in claim 5, wherein said first differential amplifier is controlled by said first control signal.

Claim 8

A source voltage control circuit as claimed in claim 1, wherein said second differential amplifying means comprises: a second single-ended N-channel input differential amplifier with two input receiving the voltage of the output node of said reference voltage generating means and said internal source voltage; a thirteenth NMOS transistor with the channel connected between said external source voltage terminal and the output node of said second differential amplifier and the gate connected to said second control signal; and a ninth PMOS transistor with the gate connected to said output node and the channel connected between said external source voltage terminal and internal source voltage terminal.

Claim 9

A source voltage control circuit as claimed in claim 7, wherein said second differential amplifier is controlled by the output of said reference voltage generating means.

Claim 10

A source voltage control circuit as claimed in claim 1, wherein said first differential amplifying means is enabled by said first control signal of "high" state so as to perform active operation, while said second differential amplifying means ius enabled by said second control signal of "low" state so as to perform stand-by operation.

Claim 11

A source voltage control circuit as claimed in claim 5, wherein said source voltage control circuit is changed form the active mode to the stand-by mode after a given delay time of said first control signal.

Claim 12

A source voltage control circuit comprising: reference voltage generating means comprising: a first NMOS transistor and diode-connected PMOS transistor with the channels connected in series between external source voltage terminal and ground voltage terminal, an output node connected to the gate of said first NMOS transistor, and a driving PMOS transistor with the channel connected between said external source voltage terminal and output node and the gate connected to the gate of said PMOS transistor; first differential amplifying means comprising: a first single-ended N-channel input differential amplifier with two inputs receiving the reference voltage of said output node and internal source voltage, a PMOS transistor with the channel connected between said external source voltage terminal and the output node of said first differential amplifier and the gate connected to a first control signal, a first and second current pass transistors with the channels connected in series between said output node and said ground voltage terminal and the gates respectively connected to the external source voltage dropped by a given value and said first control signal, and a driving transistor with the channel connected between said external source voltage terminal and said internal source voltage terminal and the gate connected to said output node; and second differential amplifying means comprising; a second single-ended N-channel input differential amplifier with two input receiving said reference voltage and said internal source voltage, an NMOS transistor with the channel connected between said external source voltage terminal and the output node of said second differential amplifier and the gate connected to said second control signal, and a driving transistor with the gate connected to said output node and the channel connected between said external source voltage terminal and said internal source voltage terminal.

Claim 13

A source voltage control circuit comprising: reference voltage generating means comprising: a first NMOS transistor and diode-connected PMOS transistor with the channels connected in series between external source voltage terminal and ground voltage terminal, an output node connected to the gate of said first NMOS transistor, and a driving PMOS transistor with the channel connected between said external source voltage terminal and output node and the gate connected to the gate of said PMOS transistor; first differential amplifying means comprising: a first single-ended N-channel input differential amplifier with two inputs receiving the reference voltage of said output node and internal source voltage, a PMOS transistor with the channel connected between said external source voltage terminal and the output node of said first differential amplifier and the gate connected to a first control signal, a first and second current pass transistors with the channels connected in series between said output node and said ground voltage terminal and the gates respectively connected to the external source voltage dropped by a given value and said first control signal, and a driving transistor with the channel connected between said external source voltage terminal and said internal source voltage terminal and the gate connected to said output node; and second differential amplifying means comprising; a second single-ended N-channel input differential amplifier with two input receiving said reference voltage and said internal source voltage, an NMOS transistor with the channel connected between said external source voltage terminal and the output node of said second differential amplifier and the gate connected to said second control signal, and a driving transistor with the gate connected to said output node and the channel connected between said external source voltage terminal and said internal source voltage terminal.

Claim 14

A source voltage control circuit as claimed in claim 11, wherein said reference voltage generating means further comprises: a resistor and pull-down PMOS transistor connected in parallel between the drain of said PMOS transistor and said ground voltage terminal; and current path means between said output node and said ground voltage terminal.

Claim 15

A source voltage control circuit as claim ed in claim 12, wherein said current path means comprises a plurality of diode-connected PMOS transistors.

Claim 16

A source voltage control circuit as claimed in claim 11, further comprising source voltage level sensing means connected between the gate of said first current path transistor and said external source voltage terminal.

Claim 17

A source voltage control circuit as claimed in claim 14, wherein said source voltage level sensing means comprises: a plurality of diode-connected NMOS transistors connected in series between said external source voltage terminal and sensing node; a resistor connected between said sensing node and said ground voltage terminal; diode-connected NMOS transistors connected in series to said sensing node; an NMOS transistor with the channel connected between said transistor and said ground voltage terminal and the gate connected to said first control signal; a diode-connected NMOS transistor connected in series between said sensing node and said ground voltage terminal; and an NMOS transistor with the gate connected to said first control signal.

Claim 18

A source voltage control circuit as claimed in claim 11, wherein said first and second current path transistors are NMOS type.

Claim 19

A source voltage control circuit as claimed in claim 16, wherein the driving transistors of said first and second differential amplifying means are PMOS.

Claim 20

A source voltage control circuit as claimed in claim 17, wherein the internal voltage slope at said internal source voltage terminal si controlled by adjusting the size of said first current path transistor when said external source voltage is equal to or greater than a specified value.

Claim 21

A source voltage control circuit as claimed in claim 11, wherein said first differential amplifying means is enabled by said first control signal of "high" state so as to perform active operation, while said second differential amplifying means is enabled by said second control signal of "low" state so as to perform stand-by operation.

Claim 22

A source voltage control circuit as claimed in claim 19, wherein said source voltage control circuit is changed form the active mode to the stand-by mode after a given delay time of said first control signal.

Claim 23

A source voltage control circuit as claimed in claim 20, wherein said first differential amplifying means is disabled when said driving transistor performs the stand-by operation.

Claim 24

A source voltage control circuit as claimed in claim 20, wherein said second differential amplifying means is disabled when said driving transistor performs the active operation.

Claim 25

A source voltage control circuit comprising: reference voltage generating means; plurality of differential amplifying means for active operation and a differential amplifying means for stand-by operation connected between an output node of said reference voltage generating means and internal source voltage terminals, respectively; gating means with the channels respectively connected between the adjacent ones of said internal voltage terminals and the gates connected to a first control signal.

Claim 26

A source voltage control circuit comprising: reference voltage generating means; plurality of differential amplifying means for active operation and a differential amplifying means for stand-by operation connected between an output node of said reference voltage generating means and internal source voltage terminals, respectively; gating means with the channels respectively connected between the adjacent ones of said internal voltage terminals and the gates connected to a first control signal.

Claim 27

A source voltage control circuit as claimed in claim 23, wherein said gating means are PMOS transistors.

Claim 28

A source voltage control circuit as claimed in claim 24, wherein said gating means are turned off in active mode and turned on in stand-by mode.