Output buffer having transmission gate and isolated supply terminals

Claim 2

A CMOS tri-state output buffer comprising: first and second relatively positive supply terminals which are isolated from one another; first and second relatively negative supply terminals which are isolated from one another; a data input terminal; a data output terminal; a predriver stage having a first pull-up transistor and a first pull-down transistor which are coupled between the first relatively positive and negative supply terminals, the first pull-up and pull-down transistors having control terminals coupled to the data input terminal and having first and second outputs, respectively; an output stage having a second pull-up transistor and a second pull-down transistor which are coupled between the second relatively positive and negative supply terminals, the second pull-up and pull-down transistors having control terminals coupled to the first and second outputs, respectively, and having third and fourth output terminals coupled to the data output terminal; an enable input terminal; an enable control circuit coupled to the enable input and having complementary output terminals; and a CMOS transmission gate coupled between the control terminals of the second pull-up and pull-down transistors and having complementary control terminals coupled to respective ones of the complementary output terminals.

Claim 3

The CMOS tri-state output buffer of claim 1 wherein the enable control circuit comprises an inverter coupled between the enable input terminal and one of the complementary output terminals and wherein the other of the complementary output terminals is coupled to the enable input terminal.

Claim 4

The CMOS tri-state output buffer of claim 1 and further comprising: a third pull-up transistor coupled to the control terminal of the second pull-up transistor and having a control terminal coupled to one of the complementary control terminals of the enable control circuit; and a third pull-down transistor coupled to the control terminal of the second pull-down transistor and having a control terminal coupled to the other complementary control terminal of the enable control circuit.

Claim 5

The CMOS tri-state output buffer of claim 3 wherein: the first, second and third pull-up transistors are p-channel CMOS transistors; and the first, second and third pull-down transistors are n-channel CMOS transistors.

Claim 6

A tri-state buffer comprising: first and second relatively positive supply terminals which are isolated from one another; first and second relatively negative supply terminals which are isolated from one another; a data input terminal; a data output terminal; an enable input terminal; a predriver stage having a first pull-up transistor and a first pull-down transistor which have control terminals coupled to the data input terminal and have first and second outputs, respectively, wherein the first pull-up and pull-down transistors are coupled between the first relatively positive and negative supply terminals; an output stage having a second pull-up transistor and a second pull-down transistor which have control terminals coupled to the first and second outputs, respectively, and which have third and fourth output terminals coupled to the data output terminal, wherein the second pull-up and pull-down transistors are coupled between the second relatively positive and negative supply terminals; means coupled between the enable input terminal and the control terminals of the second pull-up and pull-down transistors for selectively placing the second pull-up and pull-down transistors in a non-conductive state as a function of an enable signal applied to the enable input terminal; and means coupled between the enable input terminal and the control terminals of the second pull-up and pull-down transistors for selectively coupling and decoupling the control terminals of the second pull-up and pull-down transistors as a function of the enable signal applied to the enable input terminal.

Claim 7

A tri-state buffer comprising: first and second relatively positive supply terminals which are isolated from one another; first and second relatively negative supply terminals which are isolated from one another; a data input terminal; a data output terminal; an enable input terminal; a predriver stage having a first pull-up transistor and a first pull-down transistor which have control terminals coupled to the data input terminal and have first and second outputs, respectively, wherein the first pull-up and pull-down transistors are coupled between the first relatively positive and negative supply terminals; an output stage having a second pull-up transistor and a second pull-down transistor which have control terminals coupled to the first and second outputs, respectively, and which have third and fourth output terminals coupled to the data output terminal, wherein the second pull-up and pull-down transistors are coupled between the second relatively positive and negative supply terminals; means coupled between the enable input terminal and the control terminals of the second pull-up and pull-down transistors for selectively placing the second pull-up and pull-down transistors in a non-conductive state as a function of an enable signal applied to the enable input terminal; and means coupled between the enable input terminal and the control terminals of the second pull-up and pull-down transistors for selectively coupling and decoupling the control terminals of the second pull-up and pull-down transistors as a function of the enable signal applied to the enable input terminal.

Claim 8

A tri-state output buffer comprising: first and second relatively positive supply terminals which are isolated from one another; first and second relatively negative supply terminals which are isolated from one another; a data input terminal; a data output terminal; an enable input terminal; a predriver stage having a first pull-up transistor and a first pull-down transistor which have control terminals coupled to the data input terminal and have first and second outputs, respectively, wherein the first pull-up and pull-down transistors are coupled between the first relatively positive and negative supply terminals; an output stage having a second pull-up transistor and a second pull-down transistor which have control terminals coupled to the first and second outputs, respectively, and which have third and fourth output terminals coupled to the data output terminal, wherein the second pull-up and pull-down transistors are coupled between the second relatively positive and negative supply terminals; and third pull-up and pull-down transistors coupled to the first and second outputs, respectively, and having control terminals, wherein the control terminal of the third pull-up transistor is coupled to the enable input terminal; an inverter coupled between the enable input terminal and the control terminal of the third pull-down transistor; and a CMOS transmission gate coupled between the first and second output terminals and having complementary control terminals, with one complementary control terminal coupled to the enable input terminal and the other complementary control terminal coupled to the inverter.

Claim 9

A tri-state output buffer comprising: first and second relatively positive supply terminals which are isolated from one another; first and second relatively negative supply terminals which are isolated from one another; a data input terminal; a data output terminal; an enable input terminal; a predriver stage having a first pull-up transistor and a first pull-down transistor which have control terminals coupled to the data input terminal and have first and second outputs, respectively, wherein the first pull-up and pull-down transistors are coupled between the first relatively positive and negative supply terminals; an output stage having a second pull-up transistor and a second pull-down transistor which have control terminals coupled to the first and second outputs, respectively, and which have third and fourth output terminals coupled to the data output terminal, wherein the second pull-up and pull-down transistors are coupled between the second relatively positive and negative supply terminals; and third pull-up and pull-down transistors coupled to the first and second outputs, respectively, and having control terminals, wherein the control terminal of the third pull-up transistor is coupled to the enable input terminal; an inverter coupled between the enable input terminal and the control terminal of the third pull-down transistor; and a CMOS transmission gate coupled between the first and second output terminals and having complementary control terminals, with one complementary control terminal coupled to the enable input terminal and the other complementary control terminal coupled to the inverter.