Semiconductor device having a floating node that can maintain a predetermined potential for long time, a semiconductor memory device having high data maintenance performance, and a method of manufacturing thereof

Claim 2

A semiconductor device comprising a semiconductor substrate, a first region of a first type conductivity formed within said semiconductor substrate, a second region of a second type conductivity formed within said semiconductor substrate, and adjacent to said first region, a third region of the first type conductivity formed within said semiconductor substrate, and adjacent to said second region, a fourth region of the second type conductivity formed within said semiconductor substrate, and adjacent to said first region, and a node electrically floating, and formed on said first and second regions in common.

Claim 3

The semiconductor device according to claim 1, further comprising: a fifth region of the second type conductivity formed within said semiconductor substrate, and adjacent to said third region, a gate insulation film formed on said third region, a gate electrode formed on said gate insulation film, a field shield insulation film formed on said fourth region, and a field shield electrode formed on said field shield insulation film.

Claim 4

The semiconductor device according to claim 1, wherein said semiconductor substrate includes first conductivity type impurities.

Claim 5

The semiconductor device according to claim 1, wherein said semiconductor substrate comprises a buried insulation layer in contact with said first to fourth regions.

Claim 6

A semiconductor device comprising: a semiconductor substrate, a first P type region formed within said semiconductor substrate, a first N type region formed within said semiconductor substrate, and adjacent to said first P type region, a second P type region formed within said semiconductor substrate, and adjacent to said first N type region, a second N type region formed within said semiconductor substrate, and adjacent to said first P type region, a node electrically floating, and formed on said first P and N type regions in common, first potential supplying means for supplying a first potential to said second N type region, and second potential supplying means for supplying a second potential lower that said first potential to said second P type region.

Claim 7

A semiconductor device comprising: a semiconductor substrate, a first P type region formed within said semiconductor substrate, a first N type region formed within said semiconductor substrate, and adjacent to said first P type region, a second P type region formed within said semiconductor substrate, and adjacent to said first N type region, a second N type region formed within said semiconductor substrate, and adjacent to said first P type region, a node electrically floating, and formed on said first P and N type regions in common, first potential supplying means for supplying a first potential to said second N type region, and second potential supplying means for supplying a second potential lower that said first potential to said second P type region.

Claim 8

A semiconductor device comprising: a semiconductor substrate, a first P type region formed within said semiconductor substrate, and maintained at an electrical floating state during a predetermined time period, a first N type region formed within said semiconductor substrate, and coupled to said first P type region, a second P type region formed within said semiconductor substrate, and adjacent to said first N type region, a second N type region formed within said semiconductor substrate, and adjacent to said first P type region, first potential supplying means for supplying a first potential to said second N type region, and second potential supplying means for supplying a second potential higher than said first potential to said second P type region, wherein said first P type region has an impurity concentration higher than that of said second N type region, and said first N type region has an impurity concentration higher than that of said second P type region.

Claim 9

A semiconductor device comprising: a semiconductor substrate, a first P type region formed within said semiconductor substrate, and maintained at an electrical floating state during a predetermined time period, a first N type region formed within said semiconductor substrate, and coupled to said first P type region, a second P type region formed within said semiconductor substrate, and adjacent to said first N type region, a second N type region formed within said semiconductor substrate, and adjacent to said first P type region, first potential supplying means for supplying a first potential to said second N type region, and second potential supplying means for supplying a second potential higher than said first potential to said second P type region, wherein said first P type region has an impurity concentration higher than that of said second N type region, and said first N type region has an impurity concentration higher than that of said second P type region.

Claim 10

The semiconductor device according to claim 6, wherein said first P type region has an impurity concentration equal to that of said first N type region.

Claim 11

The semiconductor device according to claim 5, wherein said first P type region has an impurity concentration equal to that of said second P type region, and said first N type region has an impurity concentration equal to that of said second N type region.

Claim 12

A semiconductor device comprising: a semiconductor substrate, a first P type region formed within said semiconductor substrate, and maintained at an electrical floating state during a predetermined time period, a first N type region formed within said semiconductor substrate, and coupled to said first P type region, a second P type region formed within said semiconductor substrate, and adjacent to said first N type region, a second N type region formed within said semiconductor substrate, and adjacent to said first P type region, first potential supplying means for supplying a first potential to said second N type region, and second potential supplying means for supplying a second potential higher than said first potential to said second P type region, wherein the product of the impurity concentrations of said first P type region and said second N type region is equal to the product of the impurity concentrations of said first N type region and said second P type region.

Claim 13

A semiconductor device comprising: a semiconductor substrate, a first P type region formed within said semiconductor substrate, and maintained at an electrical floating state during a predetermined time period, a first N type region formed within said semiconductor substrate, and coupled to said first P type region, a second P type region formed within said semiconductor substrate, and adjacent to said first N type region, a second N type region formed within said semiconductor substrate, and adjacent to said first P type region, first potential supplying means for supplying a first potential to said second N type region, and second potential supplying means for supplying a second potential higher than said first potential to said second P type region, wherein the product of the impurity concentrations of said first P type region and said second N type region is equal to the product of the impurity concentrations of said first N type region and said second P type region.

Claim 14

A semiconductor device comprising: a semiconductor substrate, a first P type region formed within said semiconductor substrate, and maintained at an electrical floating state during a predetermined time period, a first N type region formed within said semiconductor substrate, and coupled to said first P type region, a second P type region formed within said semiconductor substrate, and adjacent to said first N type region, a second N type region formed within said semiconductor substrate, and adjacent to said first P type region, first potential supplying means for supplying a first potential to said second N type region, and second potential supplying means for supplying a second potential higher than said first potential to said second P type region, wherein a reverse bias voltage applied between said first P type region and said second N type region is equal to a reverse bias voltage applied between said second N type region and said second P type region.

Claim 15

A semiconductor device comprising: a semiconductor substrate, a first P type region formed within said semiconductor substrate, and maintained at an electrical floating state during a predetermined time period, a first N type region formed within said semiconductor substrate, and coupled to said first P type region, a second P type region formed within said semiconductor substrate, and adjacent to said first N type region, a second N type region formed within said semiconductor substrate, and adjacent to said first P type region, first potential supplying means for supplying a first potential to said second N type region, and second potential supplying means for supplying a second potential higher than said first potential to said second P type region, wherein a reverse bias voltage applied between said first P type region and said second N type region is equal to a reverse bias voltage applied between said second N type region and said second P type region.

Claim 16

A dynamic semiconductor memory device comprising: a semiconductor substrate, a word line formed on said semiconductor substrate, a bit line formed on said semiconductor substrate and crossing said word line, a first region of a first type conductivity formed within said semiconductor substrate, a transistor including (a) a first source/drain region of a second type conductivity formed within said semiconductor substrate, and adjacent to said first region, (b) a body region of the first type conductivity formed within said semiconductor substrate, and adjacent to said first source/drain region, (c) a second source/drain region of a second type conductivity formed within said semiconductor substrate, adjacent to said body region, and coupled to said bit line, (d) a gate insulation film formed on said body region, and (e) a gate electrode formed on said gate insulation film, and coupled to said word line, a second region of the second type conductivity formed within said semiconductor substrate, and adjacent to said first region, and a capacitor including (a) a storage node formed on said first and second regions in common, (b) a dielectric film formed on said storage node, and (c) a cell plate formed on said dielectric film.

Claim 17

A dynamic semiconductor memory device comprising: a semiconductor substrate, a word line formed on said semiconductor substrate, a bit line formed on said semiconductor substrate and crossing said word line, a first region of a first type conductivity formed within said semiconductor substrate, a transistor including (a) a first source/drain region of a second type conductivity formed within said semiconductor substrate, and adjacent to said first region, (b) a body region of the first type conductivity formed within said semiconductor substrate, and adjacent to said first source/drain region, (c) a second source/drain region of a second type conductivity formed within said semiconductor substrate, adjacent to said body region, and coupled to said bit line, (d) a gate insulation film formed on said body region, and (e) a gate electrode formed on said gate insulation film, and coupled to said word line, a second region of the second type conductivity formed within said semiconductor substrate, and adjacent to said first region, and a capacitor including (a) a storage node formed on said first and second regions in common, (b) a dielectric film formed on said storage node, and (c) a cell plate formed on said dielectric film.

Claim 18

The dynamic semiconductor memory device according to claim 11, further comprising: a field shield insulation film formed on said second region, and a field electrode formed on said field shield insulation film.

Claim 19

The dynamic semiconductor memory device according to claim 11, further comprising: first potential supplying means for supplying a first potential to said second region, and second potential supplying means for supplying a second potential different from said first potential so that reverse bias voltages are respectively applied between said first and second regions, and between said first source/drain region and said body region.

Claim 20

The dynamic semiconductor memory device according to claim 11, wherein said semiconductor substrate comprises a buried insulation layer in contact with bottoms of said first and second regions, said first and second source/drain regions, and said body region.

Claim 21

A dynamic semiconductor memory device comprising: an SOI substrate including (a) an insulation layer buried therein, and (b) an SOI active layer formed on said insulation layer, a word line formed on said SOI substrate, a bit line formed on aid SOI substrate, and crossing said word line, a first region of a first type conductivity formed within said SOI active layer, a transistor including (a) a first source/drain region of a second type conductivity formed within said SOI active layer, and adjacent to said first region, (b) a body region of the first type conductivity formed within said SOI active layer, and adjacent to said first source/drain region, (c) a second source/drain region of the second type conductivity formed within said SOI active layer, adjacent to said body region, and coupled to said bit line, (d) a gate insulation film formed on said body region, and (e) a gate electrode formed on said gate insulation film, and coupled to said word line, a second region of the second type conductivity formed within said SOI active layer, and adjacent to said first region, and a capacitor including (a) a storage node formed on said first and second regions in common, (b) a dielectric film formed on said storage node, and (c) a cell plate formed on said dielectric film.

Claim 22

A dynamic semiconductor memory device comprising: an SOI substrate including (a) an insulation layer buried therein, and (b) an SOI active layer formed on said insulation layer, a word line formed on said SOI substrate, a bit line formed on aid SOI substrate, and crossing said word line, a first region of a first type conductivity formed within said SOI active layer, a transistor including (a) a first source/drain region of a second type conductivity formed within said SOI active layer, and adjacent to said first region, (b) a body region of the first type conductivity formed within said SOI active layer, and adjacent to said first source/drain region, (c) a second source/drain region of the second type conductivity formed within said SOI active layer, adjacent to said body region, and coupled to said bit line, (d) a gate insulation film formed on said body region, and (e) a gate electrode formed on said gate insulation film, and coupled to said word line, a second region of the second type conductivity formed within said SOI active layer, and adjacent to said first region, and a capacitor including (a) a storage node formed on said first and second regions in common, (b) a dielectric film formed on said storage node, and (c) a cell plate formed on said dielectric film.

Claim 23

The dynamic semiconductor memory device according to claim 15, further comprising: a field shield insulation film formed on said second region, and a field shield electrode formed on said field shield insulation film.

Claim 24

The dynamic semiconductor memory device according to claim 15, further comprising: first potential supplying means for supplying a first potential to said second region, and second potential supplying means for supplying a second potential different from said first potential so that reverse bias voltages are respectively supplied between said first and second region, and between said first source/drain region and said body region.

Claim 25

The dynamic semiconductor memory device according to claim 16, further comprising: an isolation region adjacent to said first and second regions, said first and second source/drain regions, and said body region.

Claim 26

The dynamic semiconductor memory device according to claim 18, wherein said isolation region includes an LOCOS isolation region.

Claim 27

A dynamic semiconductor memory device comprising: an SOI substrate including (a) an insulation layer buried therein, and (b) an SOI active layer formed on said insulation layer, a word line formed on said SOI substrate, a bit line formed on said SOI substrate, and crossing said word line, a first region of a first type conductivity formed within said SOI active layer, a transistor including (a) a first source/drain region of a second type conductivity formed within said SOI active layer, and adjacent to said first region, (b) a body region of the first type conductivity formed within said SOI active layer, and adjacent to said first source/drain region, (c) a second source/drain region of the second type conductivity formed within said SOI active layer, adjacent to said body region, and coupled to said bit line, (d) a gate insulation film formed on said body region, and (e) a gate electrode formed on said gate insulation film, and coupled to said word line, a capacitor including (a) a storage node coupled to said first region and said first source/drain region, (b) a dielectric film formed on said storage node, and (c) a cell plate formed on said dielectric film, a second region of the second type conductivity formed within said SOI active layer, and adjacent to said first region, a field shield insulation film formed on said second region, a field shield electrode formed on said field shield insulation film, and an isolation region adjacent to said first and second regions, said first and second source/drain regions, and said body region, wherein said isolation region includes a mesa isolation region formed by partially etching said SOI active layer.

Claim 28

A dynamic semiconductor memory device comprising: an SOI substrate including (a) an insulation layer buried therein, and (b) an SOI active layer formed on said insulation layer, a word line formed on said SOI substrate, a bit line formed on said SOI substrate, and crossing said word line, a first region of a first type conductivity formed within said SOI active layer, a transistor including (a) a first source/drain region of a second type conductivity formed within said SOI active layer, and adjacent to said first region, (b) a body region of the first type conductivity formed within said SOI active layer, and adjacent to said first source/drain region, (c) a second source/drain region of the second type conductivity formed within said SOI active layer, adjacent to said body region, and coupled to said bit line, (d) a gate insulation film formed on said body region, and (e) a gate electrode formed on said gate insulation film, and coupled to said word line, a capacitor including (a) a storage node coupled to said first region and said first source/drain region, (b) a dielectric film formed on said storage node, and (c) a cell plate formed on said dielectric film, a second region of the second type conductivity formed within said SOI active layer, and adjacent to said first region, a field shield insulation film formed on said second region, a field shield electrode formed on said field shield insulation film, and an isolation region adjacent to said first and second regions, said first and second source/drain regions, and said body region, wherein said isolation region includes a mesa isolation region formed by partially etching said SOI active layer.

Claim 29

A dynamic semiconductor memory device comprising: an SOI substrate including (a) an insulation layer buried therein, and (b) an SOI active layer formed on said insulation layer, a word line formed on said SOI substrate, a bit line formed on said SOI substrate, and crossing said word line, a first region of a first type conductivity formed within said SOI active layer, a transistor including (a) a first source/drain region of a second type conductivity formed within said SOI active layer, and adjacent to said first region, (b) a body region of the first type conductivity formed within said SOI active layer, and adjacent to said first source/drain region, (c) a second source/drain region of the second type conductivity formed within said SOI active layer, adjacent to said body region, and coupled to said bit line, (d) a gate insulation film formed on said body region, and (e) a gate electrode formed on said gate insulation film, and coupled to said word line, a capacitor including (a) a storage node coupled to said first region and said first source/drain region, (b) a dielectric film formed on said storage node, and (c) a cell plate formed on said dielectric film, a second region of the second type conductivity formed within said SOI active layer and adjacent to said first region, a field shield insulation film formed on said second region, a field shield electrode formed on said field shield insulation film, and an isolation region adjacent to said first and second regions, said first and second source/drain regions, and said body region, wherein said isolation region comprises a trench through said SOI active layer and reaching said buried insulation layer, and an insulation film formed within said trench.

Claim 30

A dynamic semiconductor memory device comprising: an SOI substrate including (a) an insulation layer buried therein, and (b) an SOI active layer formed on said insulation layer, a word line formed on said SOI substrate, a bit line formed on said SOI substrate, and crossing said word line, a first region of a first type conductivity formed within said SOI active layer, a transistor including (a) a first source/drain region of a second type conductivity formed within said SOI active layer, and adjacent to said first region, (b) a body region of the first type conductivity formed within said SOI active layer, and adjacent to said first source/drain region, (c) a second source/drain region of the second type conductivity formed within said SOI active layer, adjacent to said body region, and coupled to said bit line, (d) a gate insulation film formed on said body region, and (e) a gate electrode formed on said gate insulation film, and coupled to said word line, a capacitor including (a) a storage node coupled to said first region and said first source/drain region, (b) a dielectric film formed on said storage node, and (c) a cell plate formed on said dielectric film, a second region of the second type conductivity formed within said SOI active layer and adjacent to said first region, a field shield insulation film formed on said second region, a field shield electrode formed on said field shield insulation film, and an isolation region adjacent to said first and second regions, said first and second source/drain regions, and said body region, wherein said isolation region comprises a trench through said SOI active layer and reaching said buried insulation layer, and an insulation film formed within said trench.

Claim 31

A dynamic semiconductor memory device comprising: an SOI substrate including (a) an insulation layer buried therein, and (b) an SOI active layer formed on said insulation layer, a word line formed on said SOI substrate, a bit line formed on said SOI substrate, and crossing said word line, a first region of a first type conductivity formed within said SOI active layer, a transistor including (a) a first source/drain region of a second type conductivity formed within said SOI active layer, and adjacent to said first region, (b) a body region of the first type conductivity formed within said SOI active layer, and adjacent to said first source/drain region, (c) a second source/drain region of the second type conductivity formed within said SOI active layer, adjacent to said body region, and coupled to said bit line, (d) a gate insulation film formed on said body region, and (e) a gate electrode formed on said gate insulation film, and coupled to said word line, a capacitor including (a) a storage node coupled to said first region and said first source/drain region, (b) a dielectric film formed on said storage node, and (c) a cell plate formed on said dielectric film, a second region of the second type conductivity formed within said SOI active layer, and adjacent to said first region, and a buffer layer formed between said first source/drain region and said first region for coupling said storage node to said first source/drain region and said first region.

Claim 32

A dynamic semiconductor memory device comprising: an SOI substrate including (a) an insulation layer buried therein, and (b) an SOI active layer formed on said insulation layer, a word line formed on said SOI substrate, a bit line formed on said SOI substrate, and crossing said word line, a first region of a first type conductivity formed within said SOI active layer, a transistor including (a) a first source/drain region of a second type conductivity formed within said SOI active layer, and adjacent to said first region, (b) a body region of the first type conductivity formed within said SOI active layer, and adjacent to said first source/drain region, (c) a second source/drain region of the second type conductivity formed within said SOI active layer, adjacent to said body region, and coupled to said bit line, (d) a gate insulation film formed on said body region, and (e) a gate electrode formed on said gate insulation film, and coupled to said word line, a capacitor including (a) a storage node coupled to said first region and said first source/drain region, (b) a dielectric film formed on said storage node, and (c) a cell plate formed on said dielectric film, a second region of the second type conductivity formed within said SOI active layer, and adjacent to said first region, and a buffer layer formed between said first source/drain region and said first region for coupling said storage node to said first source/drain region and said first region.

Claim 33

The dynamic semiconductor memory device according to claim 22, wherein said buffer layer is formed of a metal layer.

Claim 34

The dynamic semiconductor memory device according to claim 22, wherein said buffer layer comprises a cylindrical metal body and a polysilicon body formed within said metal body.

Claim 35

A dynamic semiconductor memory device comprising: an SOI substrate including an insulation layer buried therein, and an SOI active layer formed on said insulation layer, a plurality of word lines formed on said SOI substrate, a plurality of bit lines crossing said word lines, a plurality of memory cells corresponding to crossings of said word lines and said bit lines, each memory cell including (a) a transistor having (a1) a body region of a first type conductivity formed within said SOI active layer, (a2) a first source/drain region of a second type conductivity within said SOI active layer, adjacent to one side of said body region, and coupled to a corresponding bit line, (a3) a second source/drain region of a second type conductivity formed within said SOI active layer, and adjacent to the other side of said body region, and (a4) a gate electrode formed on said body region, and coupled to a corresponding word line, (b) a first region of a first type conductivity formed within said SOI active layer, and adjacent to said second source/drain region, and (c) a capacitor having a storage node formed on said second source/drain region and said first region in common, and a plurality of field shield isolation regions along said word lines, and each including (a) a second region of a second type conductivity formed within said SOI active layer, commonly adjacent to the corresponding first regions adjacent to the corresponding second source/drain regions of the corresponding transistors coupled to a corresponding one of said word lines, and (b) a field shield electrode formed on said second region.

Claim 36

A dynamic semiconductor memory device comprising: an SOI substrate including an insulation layer buried therein, and an SOI active layer formed on said insulation layer, a plurality of word lines formed on said SOI substrate, a plurality of bit lines crossing said word lines, a plurality of memory cells corresponding to crossings of said word lines and said bit lines, each memory cell including (a) a transistor having (a1) a body region of a first type conductivity formed within said SOI active layer, (a2) a first source/drain region of a second type conductivity within said SOI active layer, adjacent to one side of said body region, and coupled to a corresponding bit line, (a3) a second source/drain region of a second type conductivity formed within said SOI active layer, and adjacent to the other side of said body region, and (a4) a gate electrode formed on said body region, and coupled to a corresponding word line, (b) a first region of a first type conductivity formed within said SOI active layer, and adjacent to said second source/drain region, and (c) a capacitor having a storage node formed on said second source/drain region and said first region in common, and a plurality of field shield isolation regions along said word lines, and each including (a) a second region of a second type conductivity formed within said SOI active layer, commonly adjacent to the corresponding first regions adjacent to the corresponding second source/drain regions of the corresponding transistors coupled to a corresponding one of said word lines, and (b) a field shield electrode formed on said second region.

Claim 37

The dynamic semiconductor memory device according to claim 25, further comprising: a plurality of device isolation regions along said bit lines, and each divided by said field shield isolation regions.

Claim 38

A dynamic semiconductor memory device comprising: an SOI substrate including an insulation layer buried therein, and an SOI active layer formed on said insulation layer, a plurality of word lines formed on said SOI substrate, a plurality of bit lines crossing said word lines, a plurality of memory cells corresponding to crossings of said word lines and said bit lines, each memory cell including (a) a transistor having (a1) a body region of a first type conductivity formed within said SOI active layer, (a2) a first source/drain region of a second type conductivity within said SOI active layer, adjacent to one side of said body region, and coupled to a corresponding bit line, (a3) a second source/drain region of a second type conductivity formed within said SOI active layer, and adjacent to the other side of said body region, and (a4) a gate electrode formed on said body region, and coupled to a corresponding word line, (b) a first region of a first type conductivity formed within said SOI active layer, and adjacent to said second source/drain region, (c) a capacitor coupled to said second source/drain region and said first region, and a field shield isolation region including (a) a second region of a second type conductivity formed within said SOI active layer along said word line, adjacent to said second source/drain regions of said transistors connected to at least one of said word lines, and (b) a field shield electrode formed on said second region, and first potential supplying means for supplying a first potential to said second region.

Claim 39

A dynamic semiconductor memory device comprising: an SOI substrate including an insulation layer buried therein, and an SOI active layer formed on said insulation layer, a plurality of word lines formed on said SOI substrate, a plurality of bit lines crossing said word lines, a plurality of memory cells corresponding to crossings of said word lines and said bit lines, each memory cell including (a) a transistor having (a1) a body region of a first type conductivity formed within said SOI active layer, (a2) a first source/drain region of a second type conductivity within said SOI active layer, adjacent to one side of said body region, and coupled to a corresponding bit line, (a3) a second source/drain region of a second type conductivity formed within said SOI active layer, and adjacent to the other side of said body region, and (a4) a gate electrode formed on said body region, and coupled to a corresponding word line, (b) a first region of a first type conductivity formed within said SOI active layer, and adjacent to said second source/drain region, (c) a capacitor coupled to said second source/drain region and said first region, and a field shield isolation region including (a) a second region of a second type conductivity formed within said SOI active layer along said word line, adjacent to said second source/drain regions of said transistors connected to at least one of said word lines, and (b) a field shield electrode formed on said second region, and first potential supplying means for supplying a first potential to said second region.

Claim 40

The dynamic semiconductor memory device according to claim 27, wherein said body regions of said transistors connected to each of said word lines are continuously formed and adjacent to each other.

Claim 41

The dynamic semiconductor memory device according to claim 28, comprising second potential supplying means for supplying a second potential different from said first potential to said continuously formed body regions so that reverse bias voltages are respectively applied between said first and second regions, and between said second source/drain region and said body region.

Claim 42

A dynamic semiconductor memory device comprising: an SOI substrate including an insulation layer buried therein, and an SOI active layer formed on said insulation layer, a plurality of word lines formed on said SOI substrate, a plurality of bit lines crossing said word lines, a plurality of memory cells corresponding to crossings of said word lines and said bit lines, each memory cell including (a) a transistor having (a1) a body region of a first type conductivity formed within said SOI active layer, (a2) a first source/drain region of a second type conductivity within said SOI active layer, adjacent to one side of said body region, and coupled to a corresponding bit line, (a3) a second source/drain region of a second type conductivity formed within said SOI active layer, and adjacent to the other side of said body region, and (a4) a gate electrode formed on said body region, and coupled to a corresponding word line, (b) a first region of a first type conductivity formed within said SOI active layer, and adjacent to said second source/drain region, (c) a capacitor coupled to said second source/drain region and said first region, and a field shield isolation region including (a) a second region of a second type conductivity formed within said SOI active layer along said word line, adjacent to said second source/drain regions of said transistors connected to at least one of said word lines, and (b) a field shield electrode formed on said second region, wherein first source/drain region of transistors in two memory cells out of said memory cells are adjacent to each other in an extending direction of said bit line, wherein a bit line corresponding to said two memory cells is in contact with said first source/drain regions adjacent to each other.

Claim 43

A dynamic semiconductor memory device comprising: an SOI substrate including an insulation layer buried therein, and an SOI active layer formed on said insulation layer, a plurality of word lines formed on said SOI substrate, a plurality of bit lines crossing said word lines, a plurality of memory cells corresponding to crossings of said word lines and said bit lines, each memory cell including (a) a transistor having (a1) a body region of a first type conductivity formed within said SOI active layer, (a2) a first source/drain region of a second type conductivity within said SOI active layer, adjacent to one side of said body region, and coupled to a corresponding bit line, (a3) a second source/drain region of a second type conductivity formed within said SOI active layer, and adjacent to the other side of said body region, and (a4) a gate electrode formed on said body region, and coupled to a corresponding word line, (b) a first region of a first type conductivity formed within said SOI active layer, and adjacent to said second source/drain region, (c) a capacitor coupled to said second source/drain region and said first region, and a field shield isolation region including (a) a second region of a second type conductivity formed within said SOI active layer along said word line, adjacent to said second source/drain regions of said transistors connected to at least one of said word lines, and (b) a field shield electrode formed on said second region, wherein first source/drain region of transistors in two memory cells out of said memory cells are adjacent to each other in an extending direction of said bit line, wherein a bit line corresponding to said two memory cells is in contact with said first source/drain regions adjacent to each other.