Patent US5590299A successfully refreshed from Google Patents.
US5590299A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Multiprocessor system bus protocol for optimized accessing of interleaved storage modules
Assignee: Samsung Electronics Co Ltd
•
Filing: 1994-10-28
•
Granted: 1996-12-31
•
Expires: 2014-10-28
Abstract
Abstract A multiprocessor information processing system has a system bus with interleaved memory modules in communication with multiple CPUs. The multiprocessor system includes a subsystem monitoring circuit which monitors the addresses requested by the local CPU. If the local CPU addresses a memory module which is different from the last accessed memory module, then the subsystem monitoring circuit initiates a request to maintain control of the system bus. In this manner, sequential write and read operations are typically made to interleaved memory modules so that the effects of module recovery time are minimized. The subsystem monitoring circuit includes a transfer count register which indicates how many data transfer cycles can be run in succession before the local CPU has to relinquish control of the system bus. In this manner, fair arbitration is assured for other CPUs contending for control of the system bus.
Inventors
- 👤 Brian R. Bennett
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 03:50
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/16; G06F13/18; G06F12/00; G06F12/02; G06F12/06; G06F12/0607; G06F12/0215
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
324 words
An information processing circuit having multiple bus mastering devices and multiple interleaved memory modules, said circuit comprising: a system bus; first and second interleaved memory modules in communication with said system bus; and first and second central processing unit (CPU) modules in communication with said interleaved memory modules via said system bus, each of said modules comprising: a CPU and a cache memory, wherein said CPU generates address requests for accessing selective ones of said interleaved memory modules, and transmits and receives data to and from said interleaved memory modules; an address decoder circuit in communication with said CPU and cache memory, wherein said address decoder circuit receives address and control data indicative of the presence of a pending address request generated by said CPU, said address and control data further indicating the number of said interleaved memory modules on said system bus; an address latch circuit which latches pending addresses generated by said CPU in response to a command from said address decoder circuit; an address comparator circuit which compares addresses output by said address latch circuit and said pending address requested by said CPU; an interleave register in communication with said CPU and said address decoder, wherein said interleave register receives data indicating the number of said interleaved memory modules on said system bus; control circuitry which receives inputs from said address comparator circuit and said interleave register and, based upon said inputs, generates a signal requesting control of said system bus when said pending address request is issued to a different memory module from the memory module accessed by the previous address request issued by said CPU; and a bus controller which receives said signal generated by said control circuitry and causes said CPU module to retain control of said system bus when said control circuitry requests control of said system bus, or releases control of said system bus when said control circuitry does not request control of said system bus.
Claim 2
Dependent Claim
324 words
An information processing circuit having multiple bus mastering devices and multiple interleaved memory modules, said circuit comprising: a system bus; first and second interleaved memory modules in communication with said system bus; and first and second central processing unit (CPU) modules in communication with said interleaved memory modules via said system bus, each of said modules comprising: a CPU and a cache memory, wherein said CPU generates address requests for accessing selective ones of said interleaved memory modules, and transmits and receives data to and from said interleaved memory modules; an address decoder circuit in communication with said CPU and cache memory, wherein said address decoder circuit receives address and control data indicative of the presence of a pending address request generated by said CPU, said address and control data further indicating the number of said interleaved memory modules on said system bus; an address latch circuit which latches pending addresses generated by said CPU in response to a command from said address decoder circuit; an address comparator circuit which compares addresses output by said address latch circuit and said pending address requested by said CPU; an interleave register in communication with said CPU and said address decoder, wherein said interleave register receives data indicating the number of said interleaved memory modules on said system bus; control circuitry which receives inputs from said address comparator circuit and said interleave register and, based upon said inputs, generates a signal requesting control of said system bus when said pending address request is issued to a different memory module from the memory module accessed by the previous address request issued by said CPU; and a bus controller which receives said signal generated by said control circuitry and causes said CPU module to retain control of said system bus when said control circuitry requests control of said system bus, or releases control of said system bus when said control circuitry does not request control of said system bus.
Claim 3
Dependent Claim
101 words
A processing circuit as defined in claim 1, wherein said CPU modules further comprise: a transfer count register which stores a transfer count value; a transfer counter which stores a counter value that is incremented each time a data transfer cycle is performed between said CPU and one of said interleaved memory modules; and a transfer count comparator circuit which compares said transfer count value stored in said transfer count register and said counter value stored in said transfer counter, and provides a terminate control signal to said bus controller if said counter value is equal to said transfer count value.
Claim 4
Dependent Claim
149 words
A monitoring subcircuit for use in a bus mastering module within a multimaster system having a system bus in communication with interleaved memory modules, and wherein said bus mastering module generates address requests on said system bus for accessing selected ones of said interleaved memory modules, said subcircuit comprising: an address locator circuit which, before a pending address is placed onto said system bus, determines if a corresponding pending address request within said bus mastering module is directed to a memory module which received an immediately preceding address request generated by said bus mastering module; and a control circuit which indicates that said bus mastering module should retain control of said system bus when said address locator circuit determines that said pending address request is directed to accessing a different memory module than said memory module which received said immediately preceding address request generated by said bus mastering module.
Claim 5
Dependent Claim
149 words
A monitoring subcircuit for use in a bus mastering module within a multimaster system having a system bus in communication with interleaved memory modules, and wherein said bus mastering module generates address requests on said system bus for accessing selected ones of said interleaved memory modules, said subcircuit comprising: an address locator circuit which, before a pending address is placed onto said system bus, determines if a corresponding pending address request within said bus mastering module is directed to a memory module which received an immediately preceding address request generated by said bus mastering module; and a control circuit which indicates that said bus mastering module should retain control of said system bus when said address locator circuit determines that said pending address request is directed to accessing a different memory module than said memory module which received said immediately preceding address request generated by said bus mastering module.
Claim 6
Dependent Claim
17 words
A monitoring subcircuit as defined in claim 3 wherein said bus mastering module comprises a processor module.
Claim 7
Dependent Claim
51 words
A monitoring subcircuit as defined in claim 3, further comprising a terminate control circuit which generates a signal indicating that said bus mastering module should release control of the bus once the bus mastering module has run a maximum number of consecutive data transfers without relinquishing control of said system bus.
Claim 8
Dependent Claim
106 words
An information processing system including multiple bus mastering modules, said system comprising: a system bus; a plurality of memory modules in communication with said system bus; and a plurality of bus mastering modules, wherein each of said bus mastering modules includes a subcircuit which, before an address directed to one of said memory modules is placed on said system bus, monitors said address requested by said bus mastering modules, and wherein said subcircuit grants the local bus mastering circuit control of the system bus for a next data transfer cycle if a current memory address is to a different memory module than a previous address request.
Claim 9
Dependent Claim
106 words
An information processing system including multiple bus mastering modules, said system comprising: a system bus; a plurality of memory modules in communication with said system bus; and a plurality of bus mastering modules, wherein each of said bus mastering modules includes a subcircuit which, before an address directed to one of said memory modules is placed on said system bus, monitors said address requested by said bus mastering modules, and wherein said subcircuit grants the local bus mastering circuit control of the system bus for a next data transfer cycle if a current memory address is to a different memory module than a previous address request.
Claim 10
Dependent Claim
22 words
An information processing system as defined in claim 6, wherein at least one of said bus mastering modules comprises a processor module.
References Cited (Backward Citations)
US4669056A
Cited
US4797815A
Cited
US4933846A
Cited
US5005151A
Cited
US5341486A
Cited
US5043874A
Cited
US5274788A
Cited
US5257356A
Cited
US5287477A
Cited
US5446847A
Cited
US5323489A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-12-31 | 2000-07-01 | 2000-12-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-12-31 | 2004-07-01 | 2004-12-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-12-31 | 2008-07-01 | 2008-12-31 | $7700.00 | Window Closed / Lapsed |