Programmable system bus priority network

Claim 1

A bus interface priority network for use on a system which includes a system bus in which requests are asynchronously transferred according to a predetermined bus protocol between a plurality of different types of units which connect to different physical positions along said system bus to access said system bus through a distributed priority network on a priority basis relative to said unit's position on said bus, said interface network being connected to one of said different physical positions and comprising: an input section coupled to receive requests from a plurality of different types of requestors for processing different types of transactions; priority network request generator means coupled to said system bus and to said input section for receiving respectively, input bus request signals indicating the presence of a higher priority request on said system bus and input request signals representative of requests from said requestors, said priority network request generator means generating output request signals and a priority network busy signal indicating a start of a bus resolution cycle of operation in response to said input bus request signals, request storage means connected to said priority network generator means, said request storage means storing said input request signals representative of requests received from said different types of requestors for resolution during said bus resolution cycle of operation; delay generation means coupled to said priority network request generator means for generating a plurality of output delay signals representative of predetermined delay intervals established for said different types of requestors to access said system bus in response to said priority network busy signal; and, request pulse generation means for generating an output bus request signal and being connected to receive said input request signals stored by said request storage means and said plurality of output delay signals from said delay generation means, said request pulse generation means including programmable array logic (PAL) circuit means programmed to select a predetermined one of said output delay signals as a function of which one of said different types of requestors is selected by said PAL circuit means as having the highest priority request according to a predetermined priority scheme for generating said output bus request signal to said distributed priority network for enabling bus access within a minimum access time for each type of transaction being processed by said different requestors sharing common access to said system bus.