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US5590075A
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Method for testing an electrically erasable and programmable memory device
Assignee: STMicroelectronics SRL
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Filing: 1995-06-07
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Granted: 1996-12-31
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Expires: 2015-06-07
Abstract
Abstract A method for testing an electrically erasable and programmable memory device comprising a matrix of memory cells and redundancy memory cells for functionally substituting defective memory cells, comprises the steps of: programing all the memory cells of the memory device; submitting all the memory cells of the memory device to a preliminary electrical erasure for a time much shorter than an average erasing time of the memory cells; reading the information stored in all the memory cells of the memory device; memorizing the addresses of defective memory cells which have been read as erased memory cell; storing the addresses of the defective memory cells in redundancy registers associated to redundancy memory cells which must substitute the defective memory cells.
Inventors
- 👤 Stefano Mazzali
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 10:04
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/70; G11C29/78; G11C29/80; G11C29/816; G11C29/82; G11C29/04; G11C29/08; G11C29/10; G11C29/12; G11C29/18; G11C29/24; G11C29/52
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
133 words
A method for in-factory testing of a flash EEPROM device comprising a matrix of memory cells and redundancy memory cells for functionally substituting defective memory cells, characterized by comprising the following steps: a) programming all the memory cells of the memory device; b) submitting all the memory cells of the memory device to a preliminary electrical erasure for a time much shorter than an average erasing time of the memory cells; c) reading the information stored in all the memory cells of the memory device; d) memorizing the addresses of defective memory cells which at step c) have been read as erased memory cell; and e) storing the addresses of the defective memory cells in redundancy registers of the memory device, associated to redundancy memory cells which must substitute the defective memory cells.
Claim 2
Independent Claim
133 words
A method for in-factory testing of a flash EEPROM device comprising a matrix of memory cells and redundancy memory cells for functionally substituting defective memory cells, characterized by comprising the following steps: a) programming all the memory cells of the memory device; b) submitting all the memory cells of the memory device to a preliminary electrical erasure for a time much shorter than an average erasing time of the memory cells; c) reading the information stored in all the memory cells of the memory device; d) memorizing the addresses of defective memory cells which at step c) have been read as erased memory cell; and e) storing the addresses of the defective memory cells in redundancy registers of the memory device, associated to redundancy memory cells which must substitute the defective memory cells.
Claim 3
Dependent Claim
28 words
The method according to claim 1, characterized in that the time duration of said preliminary electrical erasure is three order of magnitude shorter than said average erasing time.
Claim 4
Dependent Claim
34 words
The method according to claim 1, characterized in that during step c) the memory device is supplied with a voltage supply substantially equal to a minimum voltage supply value admissible for the memory device.
Claim 5
Dependent Claim
38 words
The method according to claim 1, characterized in that between step a) and step b) there is performed a verify step providing for reading of the information stored in all the memory cells to verify their programing state.
Claim 6
Dependent Claim
35 words
The method according to claim 4, characterized in that during the verify step the memory device is supplied with a voltage supply substantially equal to a minimum voltage supply value admissible for the memory device.
Claim 7
Dependent Claim
35 words
The method according to claim 1, characterized in that between steps d) and e) there is performed an electrical erasure of all the memory cells for a time substantially equal to said average erasing time.
Claim 8
Independent Claim
70 words
A method of testing an electrically erasable memory device, comprising: subjecting matrix memory cells of said memory device to a programming routine; implementing upon said cells an electrical erasing routine for a duration that is substantially less than the time required to insure substantially full erasure of said cells; reading said cells; identifying as defective those cells that are erased; and substituting for each defective cell a redundant memory cell.
Claim 9
Independent Claim
70 words
A method of testing an electrically erasable memory device, comprising: subjecting matrix memory cells of said memory device to a programming routine; implementing upon said cells an electrical erasing routine for a duration that is substantially less than the time required to insure substantially full erasure of said cells; reading said cells; identifying as defective those cells that are erased; and substituting for each defective cell a redundant memory cell.
Claim 10
Dependent Claim
27 words
The method of claim 7 wherein said duration is approximately three orders of magnitude less than said time required to insure substantially full erasure of said cells.
Claim 11
Dependent Claim
19 words
The method of claim 7, further comprising, after said subjecting, verifying that said cells are in a programmed state.
Claim 12
Dependent Claim
27 words
The method of claim 9 wherein said verifying comprises supplying said memory device with a supply voltage substantially equal to the minimum supply voltage said device requires.
Claim 13
Dependent Claim
34 words
The method of claim 7, further comprising, after said identifying, subjecting said cells to said erasing routine for a duration substantially equal to said time required to insure substantially full erasure of said cells.
Claim 14
Dependent Claim
34 words
The method of claim 7 wherein said reading comprises supplying said memory device with a supply voltage that is substantially equal to the minimum supply voltage required to insure proper operation of said device.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-12-31 | 2000-07-01 | 2000-12-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-12-31 | 2004-07-01 | 2004-12-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-12-31 | 2008-07-01 | 2008-12-31 | $7700.00 | Window Closed / Lapsed |