Patent US5587945A successfully refreshed from Google Patents.
US5587945A
Expired / Lapsed
US
⏱️ 0.0 years remaining
CMOS EEPROM cell with tunneling window in the read path
Assignee: Lattice Semiconductor Corp
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Filing: 1995-11-06
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Granted: 1996-12-24
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Expires: 2015-11-06
Abstract
Abstract A CMOS memory cell including PMOS and NMOS transistors with a common floating gate. The CMOS memory cell includes a first capacitor connecting a first control voltage to the common floating gate and a second tunneling capacitor connected from the common floating gate to the source of the NMOS transistor. The tunneling capacitor includes a tunneling oxide region utilized to charge or discharge the floating gate during program or erase. The CMOS cell further includes a pass transistor with a source to drain path connecting the source of the NMOS transistor to a second control voltage.
Inventors
- 👤 Jonathan Lin
- 👤 Jack Z. Peng
- 👤 Radu Barsan
- 👤 Sunil Mehta
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 17:55
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/04; G11C16/0408; G11C16/0441; G11C16/045; H; H10; H10B; H10B69/00; G11C2216/00; G11C2216/02; G11C2216/10
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
104 words
A memory cell comprising: a PMOS transistor having a drain forming an output node, a source and a channel between the source and drain underlying a common floating gate; an NMOS transistor having a drain coupled to the output node, a source and a channel between the source and drain of the NMOS transistor underlying the common floating gate; a capacitor having a first terminal forming a control gate and a second terminal coupled to the common floating gate; a tunneling capacitor having a first terminal coupled to the common floating gate and a second terminal coupled to the source of the NMOS transistor.
Claim 2
Dependent Claim
104 words
A memory cell comprising: a PMOS transistor having a drain forming an output node, a source and a channel between the source and drain underlying a common floating gate; an NMOS transistor having a drain coupled to the output node, a source and a channel between the source and drain of the NMOS transistor underlying the common floating gate; a capacitor having a first terminal forming a control gate and a second terminal coupled to the common floating gate; a tunneling capacitor having a first terminal coupled to the common floating gate and a second terminal coupled to the source of the NMOS transistor.
Claim 3
Dependent Claim
42 words
The memory cell of claim 1 further comprising: a pass transistor having a gate for receiving a word line (WL) select voltage, a drain coupled to the source of the NMOS transistor and a source for receiving a word control (WC) voltage.
Claim 4
Dependent Claim
14 words
The memory cell of claim 2 wherein the pass transistor is an NMOS transistor.
Claim 5
Dependent Claim
72 words
A method of programming the CMOS memory cell of claim 1, wherein programming results in electrons being removed from the common floating gate, programming comprising the steps of: applying a voltage between the control gate and the second terminal of the tunneling capacitor so that electrons transfer from the common floating gate to the second terminal of the tunneling capacitor; and creating a high impedance at the source of the PMOS transistor.
Claim 6
Dependent Claim
72 words
A method of erasing the CMOS memory cell of claim 1, wherein erasing results in electrons being added to the common floating gate, erasing comprising the steps of: applying a voltage between the control gate and the second terminal of the tunneling capacitor so that electrons transfer from the second terminal of the tunneling capacitor to the common floating gate; and creating a high impedance at the source of the PMOS transistor.
Claim 7
Dependent Claim
159 words
A programmable logic device (PLD) comprising: a sense amplifier having a product term (PT) input and a product term ground (PTG) input; a plurality of memory cells, each comprising: a PMOS transistor having a drain coupled to the PT line, a source and a channel between the source and drain underlying a common floating gate; an NMOS transistor having a drain coupled to the PT line, a source and a channel between the source and drain of the NMOS transistor underlying the common floating gate; a capacitor having a first terminal forming a control gate and a second terminal coupled to the common floating gate; a tunneling capacitor having a first terminal coupled to the common floating gate and a second terminal coupled to the source of the NMOS transistor; and a pass transistor having a drain connected to the source of the NMOS transistor, a source connected to the PTG line, and a gate forming an enable input.
Claim 8
Dependent Claim
159 words
A programmable logic device (PLD) comprising: a sense amplifier having a product term (PT) input and a product term ground (PTG) input; a plurality of memory cells, each comprising: a PMOS transistor having a drain coupled to the PT line, a source and a channel between the source and drain underlying a common floating gate; an NMOS transistor having a drain coupled to the PT line, a source and a channel between the source and drain of the NMOS transistor underlying the common floating gate; a capacitor having a first terminal forming a control gate and a second terminal coupled to the common floating gate; a tunneling capacitor having a first terminal coupled to the common floating gate and a second terminal coupled to the source of the NMOS transistor; and a pass transistor having a drain connected to the source of the NMOS transistor, a source connected to the PTG line, and a gate forming an enable input.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-12-24 | 2000-06-24 | 2000-12-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-12-24 | 2004-06-24 | 2004-12-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-12-24 | 2008-06-24 | 2008-12-24 | $7700.00 | Window Closed / Lapsed |