Patent US6943602B1 successfully refreshed from Google Patents.
US5587329A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method for fabricating a switching transistor having a capacitive network proximate a drift region
Assignee: Sarnoff Corp
•
Filing: 1994-08-24
•
Granted: 1996-12-24
•
Expires: 2014-08-24
Abstract
Abstract In an active matrix electroluminescent display, a pixel containing a grounded conductive electric field shield between an EL cell and the switching electronics for the EL cell. In a method of fabricating the pixel, first, an EL cell switching circuit is formed, then an insulating layer is formed over the switching circuit and a conductive layer (the field shield) is formed over the insulating layer. A through hole is provided in the field shield such that an electrical connection can be made between the switching circuit and an EL cell. The EL cell is then conventionally formed on top of the shield layer. Consequently, the shield isolates the switching circuit from the EL cell and ensures that any electric fields produced in the EL cell do not interfere with the operation of the switching electronics. Furthermore, the switching circuitry for each cell contains two transistors; a low voltage MOS transistor and a high voltage MOS transistor. The low voltage transistor is controlled by signals on a data and a select line. When activated, the low voltage transistor activates the high voltage transistor by charging the gate of the high voltage transistor. This gate charge is stored between the gate electrode of the high voltage transistor and the electric field shield. Additionally, to improve the breakdown voltage of the high voltage transistor, a capacitive divider network is fabricated proximate the drift region of that transistor. As such, the network uniformly distributes an electric field over the drift region.
Inventors
- 👤 Fu-Lung Hseuh
- 👤 Alfred C. Ipri
- 👤 Gary M. Dolny
- 👤 Roger G. Stewart
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 16:46
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D86/00; H10D86/201; G; G09; G09G; G09G3/00; G09G3/20; G09G3/22; G09G3/30; H10D84/02; H10D84/03; H10D84/038; H10D84/80; H10D84/82; H10D84/83; H10P; H10P58/00; G09G2300/00; G09G2300/08; G09G2300/0809; G09G2300/0842
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
215 words
A method of fabricating a high voltage transistor having a uniform electric field within a drift region comprising the steps of: forming, upon a substrate, a drift region for a transistor; forming a drain region and a source region for said transistor, where said drift region is located between said drain region and said source region; forming an insulating layer over said drift region; depositing a gate electrode on said insulating layer, said gate electrode partially overlapping said drift region; depositing a first plurality of capacitive elements on said insulating layer, said elements overlapping a portion of said drift region not overlapped by said gate electrode; forming a second insulating layer over said capacitive elements and said gate electrode; depositing a second plurality of capacitive elements on said second insulating layer, said second plurality of elements partially overlaps said first plurality of capacitive elements; forming a third insulating layer over said second plurality of capacitive elements; and depositing a high voltage electrode on said third insulating layer in a location overlying said first and second pluralities of capacitive elements such that, when a high voltage is applied to said high voltage electrode, a charge accumulates on said first and second plurality of capacitive elements and an electric field is uniformly distributed in said drift region.
Claim 2
Independent Claim
215 words
A method of fabricating a high voltage transistor having a uniform electric field within a drift region comprising the steps of: forming, upon a substrate, a drift region for a transistor; forming a drain region and a source region for said transistor, where said drift region is located between said drain region and said source region; forming an insulating layer over said drift region; depositing a gate electrode on said insulating layer, said gate electrode partially overlapping said drift region; depositing a first plurality of capacitive elements on said insulating layer, said elements overlapping a portion of said drift region not overlapped by said gate electrode; forming a second insulating layer over said capacitive elements and said gate electrode; depositing a second plurality of capacitive elements on said second insulating layer, said second plurality of elements partially overlaps said first plurality of capacitive elements; forming a third insulating layer over said second plurality of capacitive elements; and depositing a high voltage electrode on said third insulating layer in a location overlying said first and second pluralities of capacitive elements such that, when a high voltage is applied to said high voltage electrode, a charge accumulates on said first and second plurality of capacitive elements and an electric field is uniformly distributed in said drift region.
Claim 3
Independent Claim
211 words
A method of fabricating a pixel within an electroluminescent display comprising the steps of: forming, upon a substrate, a drift region for a transistor; forming a drain region and a source region for said transistor, where said drift region is located between said drain region and said source region; forming a first insulating layer over said drift region; depositing a gate electrode on said first insulating layer, said gate electrode partially overlapping said drift region; depositing a first plurality of capacitive elements on said insulating layer, said elements overlapping a portion of said drift region not overlapped by said gate electrode; forming a second insulating layer over said capacitive elements and said gate electrode; depositing a second plurality of capacitive elements on said second insulating layer, said second plurality of elements partially overlaps said first plurality of capacitive elements; forming a third insulating layer over said second plurality of capacitive elements; depositing a high voltage electrode of an electroluminescent cell on said third insulating layer such that, when a high voltage is applied to said high voltage electrode, a charge accumulates on said first and second plurality of capacitive elements and an electric field is uniformly distributed in said drift region; and forming said electroluminescent cell on said high voltage electrode.
Claim 4
Independent Claim
211 words
A method of fabricating a pixel within an electroluminescent display comprising the steps of: forming, upon a substrate, a drift region for a transistor; forming a drain region and a source region for said transistor, where said drift region is located between said drain region and said source region; forming a first insulating layer over said drift region; depositing a gate electrode on said first insulating layer, said gate electrode partially overlapping said drift region; depositing a first plurality of capacitive elements on said insulating layer, said elements overlapping a portion of said drift region not overlapped by said gate electrode; forming a second insulating layer over said capacitive elements and said gate electrode; depositing a second plurality of capacitive elements on said second insulating layer, said second plurality of elements partially overlaps said first plurality of capacitive elements; forming a third insulating layer over said second plurality of capacitive elements; depositing a high voltage electrode of an electroluminescent cell on said third insulating layer such that, when a high voltage is applied to said high voltage electrode, a charge accumulates on said first and second plurality of capacitive elements and an electric field is uniformly distributed in said drift region; and forming said electroluminescent cell on said high voltage electrode.
Claim 5
Dependent Claim
38 words
The method of claim 2 further comprising the steps of: forming, upon said second insulating layer and overlapping said gate electrode, an electric field shield that isolates an electric field within said electroluminescent cell from said gate electrode.
Claim 6
Independent Claim
226 words
A method of fabricating a pixel within an electroluminescent display comprising the steps of: forming, upon a substrate, a drift region for a transistor; forming a drain region and a source region for said transistor, where said drift region is located between said drain region and said source region; forming a first insulating layer over said drift region; depositing a gate electrode on said first insulating layer, said gate electrode partially overlapping said drift region; depositing a first plurality of capacitive elements on said insulating layer, said elements overlapping a portion of said drift region not overlapped by said gate electrode; forming a second insulating layer over said capacitive elements and said gate electrode; depositing a second plurality of capacitive elements on said second insulating layer, said second plurality of elements partially overlaps said first plurality of capacitive elements; forming, upon said second insulating slayer and overlapping said gate electrode, an electric field shield; forming a third insulating layer over said second plurality of capacitive elements; depositing a high voltage electrode of an electroluminescent cell on said third insulating layer such that, when a high voltage is applied to said high voltage electrode, a charge accumulates on said first and second plurality of capacity element and an electric field is uniformly distributed in said drift region; and forming said electroluminescent cell upon said high voltage electrode.
Claim 7
Independent Claim
226 words
A method of fabricating a pixel within an electroluminescent display comprising the steps of: forming, upon a substrate, a drift region for a transistor; forming a drain region and a source region for said transistor, where said drift region is located between said drain region and said source region; forming a first insulating layer over said drift region; depositing a gate electrode on said first insulating layer, said gate electrode partially overlapping said drift region; depositing a first plurality of capacitive elements on said insulating layer, said elements overlapping a portion of said drift region not overlapped by said gate electrode; forming a second insulating layer over said capacitive elements and said gate electrode; depositing a second plurality of capacitive elements on said second insulating layer, said second plurality of elements partially overlaps said first plurality of capacitive elements; forming, upon said second insulating slayer and overlapping said gate electrode, an electric field shield; forming a third insulating layer over said second plurality of capacitive elements; depositing a high voltage electrode of an electroluminescent cell on said third insulating layer such that, when a high voltage is applied to said high voltage electrode, a charge accumulates on said first and second plurality of capacity element and an electric field is uniformly distributed in said drift region; and forming said electroluminescent cell upon said high voltage electrode.
References Cited (Backward Citations)
US4006383A
Cited
US4087792A
Cited
US4532506A
Cited
US4528480A
Cited
US4602192A
Cited
US4601097A
Cited
US4737684A
Cited
US4983880A
Cited
US4876212A
Cited
US5020881A
Cited
US5309060A
Cited
US5032531A
Cited
US4954747A
Cited
US4908328A
Cited
US5189500A
Cited
US5118987A
Cited
US5095248A
Cited
US5056895A
Cited
US5258320A
Cited
US5198721A
Cited
US5308779A
Cited
US5057450A
Cited
US5302966A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-12-24 | 2000-06-24 | 2000-12-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-12-24 | 2004-06-24 | 2004-12-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-12-24 | 2008-06-24 | 2008-12-24 | $7700.00 | Window Closed / Lapsed |