US5586253A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method and apparatus for validating I/O addresses in a fault-tolerant computer system
Assignee: Ascend Communications Inc
•
Filing: 1994-12-15
•
Granted: 1996-12-17
•
Expires: 2014-12-15
Abstract
Abstract A novel mapping and protection circuit arrangement comprises a plurality of checking mechanisms that collectively cooperate to verify the accuracy of I/O addresses generated by input/output (I/O) controllers of a fault-tolerant computer. These verified I/O addresses are translated into system addresses to enable direct memory access (DMA) transactions between the controllers and the computer's host memory. Specifically, certain of the checking mechanisms cooperate to ensure that the DMA accesses are directed to correct pages in host memory, while other checking mechanisms are provided to ensure that memory access operations are performed at correct locations within the page. Additional checking mechanisms are provided to further verify the accuracy of generated I/O addresses.
Inventors
- 👤 Gregory M. Green
- 👤 Steven Kohalmi
- 👤 Karen R. Bricknell
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 12:02
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/14; G06F11/1402; G06F11/1405; G06F11/141
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
105 words
A method for verifying the accuracy of an input/output (I/O) virtual address (IOVA) generated by an I/O controller of a fault-tolerant computer in anticipation of a direct memory access (DMA) transaction between a host memory and the I/O controller, the method comprising the steps of: apportioning the IOVA into a plurality of fields including a page & line offset field having two least significant bits comprising byte-enable bits; translating said byte-enable bits into byte-enable signals; comparing states of said byte-enable signals with contents of a byte-enable combination table; and verifying the states of said byte-enable signals in response to a non-match in said comparing step.
Claim 2
Independent Claim
105 words
A method for verifying the accuracy of an input/output (I/O) virtual address (IOVA) generated by an I/O controller of a fault-tolerant computer in anticipation of a direct memory access (DMA) transaction between a host memory and the I/O controller, the method comprising the steps of: apportioning the IOVA into a plurality of fields including a page & line offset field having two least significant bits comprising byte-enable bits; translating said byte-enable bits into byte-enable signals; comparing states of said byte-enable signals with contents of a byte-enable combination table; and verifying the states of said byte-enable signals in response to a non-match in said comparing step.
Claim 3
Dependent Claim
120 words
Apparatus for verifying the accuracy of an input/output (I/O) virtual address (IOVA) generated by an I/O controller of a fault-tolerant computer in anticipation of a direct memory access (DMA) transaction between a host memory and the I/O controller, the apparatus comprising: means for apportioning the IOVA into a plurality of fields including a page & line offset field having two least significant bits comprising byte-enable bits; means, coupled to said apportioning means, for translating said byte-enable bits into byte-enable signals; means, coupled to said translating means, for comparing the states of said byte-enable signals with contents of a byte-enable combination table; and means for verifying the states of said byte-enable signals in response to said comparing means producing a non-match.
Claim 4
Dependent Claim
120 words
Apparatus for verifying the accuracy of an input/output (I/O) virtual address (IOVA) generated by an I/O controller of a fault-tolerant computer in anticipation of a direct memory access (DMA) transaction between a host memory and the I/O controller, the apparatus comprising: means for apportioning the IOVA into a plurality of fields including a page & line offset field having two least significant bits comprising byte-enable bits; means, coupled to said apportioning means, for translating said byte-enable bits into byte-enable signals; means, coupled to said translating means, for comparing the states of said byte-enable signals with contents of a byte-enable combination table; and means for verifying the states of said byte-enable signals in response to said comparing means producing a non-match.
References Cited (Backward Citations)
US3192362A
Cited
US4677546A
Cited
US4637024A
Cited
US4942519A
Cited
US4777575A
Cited
US4774659A
Cited
US5115490A
Cited
US5276823A
Cited
US5321706A
Cited
US5371868A
Cited
US5392302A
Cited
US5426747A
Cited
US5463755A
Cited
US5357615A
Cited
US5404361A
Cited
US5440710A
Cited
US5449849A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-12-17 | 2000-06-17 | 2000-12-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-12-17 | 2004-06-17 | 2004-12-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-12-17 | 2008-06-17 | 2008-12-17 | $7700.00 | Window Closed / Lapsed |