US5404361A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method and apparatus for ensuring data integrity in a dynamically mapped data storage subsystem
Assignee: Storage Technology Corp
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Filing: 1992-07-27
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Granted: 1995-04-04
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Expires: 2012-07-27
Abstract
Abstract The dynamically mapped data storage subsystem generates a two error correction, three error detection code of extent sufficient to cover not only the data but also the corresponding memory address for each data record stored therein. The error correction code is transmitted and stored with the data within the data storage subsystem to ensure the integrity of both the data and its memory address.
Inventors
- 👤 Anthony J. Casorso
- 👤 David P. Haldeman
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 11:53
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/08; G06F11/10; G06F11/1076; G11; G11B; G11B20/00; G11B20/10; G11B20/18; G11B20/1833; G06F2201/00; G06F2201/815; G06F2211/00; G06F2211/10; G06F2211/1002; G06F2211/1007
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
124 words
In a data storage subsystem, a memory for storing data records received from a host processor, comprising: a plurality of memory devices for storing data records received from a host processor; means, responsive to the receipt of a data record from said host processor, for generating a memory address to identify available memory space in a selected one of said memory devices to store said received data record thereon; means for generating a multi-bit error detecting and correcting code across both said received data record and said generated memory address; and means for writing said received data record and said generated multi-bit error detecting and correcting code associated with said received data record in said available memory space in said selected one memory device.
Claim 2
Dependent Claim
124 words
In a data storage subsystem, a memory for storing data records received from a host processor, comprising: a plurality of memory devices for storing data records received from a host processor; means, responsive to the receipt of a data record from said host processor, for generating a memory address to identify available memory space in a selected one of said memory devices to store said received data record thereon; means for generating a multi-bit error detecting and correcting code across both said received data record and said generated memory address; and means for writing said received data record and said generated multi-bit error detecting and correcting code associated with said received data record in said available memory space in said selected one memory device.
Claim 3
Dependent Claim
145 words
The system of claim 1 further comprising: means, responsive to the subsequent receipt from said host processor of a request to read a data record from said data storage subsystem, for generating a memory address indicative of a memory location on one of said memory devices on which said requested data record is written; means for retrieving said requested data record from said one memory device using said generated requested data record memory address; means for retrieving a multi-bit error detecting and correcting code, stored with said requested data record, from said one memory device; and means for comparing said generated requested data record memory address and said requested data record with said retrieved multi-bit error detecting and correcting code, stored with said requested data record to determine whether errors are contained in said generated requested data record memory address and said requested data record.
Claim 4
Dependent Claim
30 words
The system of claim 2 further comprising: means for identifying a bit location in said generated requested data record memory address and said requested data record that is in error.
Claim 5
Dependent Claim
71 words
The system of claim 1 further comprising: means in each said memory device responsive to the receipt of a data record and said generated multi-bit error detecting and correcting code associated with said received data record for comparing said generated memory address and said received data record with said multi-bit error detecting and correcting code to determine whether errors are contained in said generated memory address and said received data record.
Claim 6
Dependent Claim
43 words
The system of claim 4 wherein each said memory device further comprises: means for generating an error indication signal indicative of a failure of said generated memory address and said received data record to match said generated multi-bit error detecting and correcting code.
Claim 7
Dependent Claim
124 words
In a data storage subsystem having a memory for storing data records received from host processor, said memory having a plurality of memory devices, a method of detecting address and data errors comprising the steps of: generating, in response to the receipt of a data record from said host processor, a memory address to identify available memory space in a selected one of said memory devices to store said received data record thereon; generating a multi-bit error detecting and correcting code across both said received data record and said generated memory address; and writing said received data record and said generated multibit error detecting and correcting code associated with said received data record in said available memory space in said selected one memory device.
Claim 8
Dependent Claim
124 words
In a data storage subsystem having a memory for storing data records received from host processor, said memory having a plurality of memory devices, a method of detecting address and data errors comprising the steps of: generating, in response to the receipt of a data record from said host processor, a memory address to identify available memory space in a selected one of said memory devices to store said received data record thereon; generating a multi-bit error detecting and correcting code across both said received data record and said generated memory address; and writing said received data record and said generated multibit error detecting and correcting code associated with said received data record in said available memory space in said selected one memory device.
Claim 9
Dependent Claim
141 words
The method of claim 6 further comprising the steps of: generating, in response to the subsequent receipt from said host processor of a request to read a data record from said data storage subsystem, a memory address indicative of a memory location on one of said memory devices on which said requested data record is written; retrieving said requested data record from said one memory device using said generated requested data record memory address; retrieving a multi-bit error detecting and correcting code, stored with said requested data record, from said one memory device; and comparing said generated requested data record memory address and said requested data record with said retrieved multi-bit error detecting and correcting code, stored with said requested data record to determine whether errors are contained in said generated requested data record memory address and said requested data record.
Claim 10
Dependent Claim
31 words
The method of claim 7 further comprising the step of: identifying a bit location in said generated requested data record memory address and said requested data record that is in error.
Claim 11
Dependent Claim
74 words
The method of claim 6 further comprising the step of: comparing, in each said memory device in response to the receipt of a data record and said generated multi-bit error detecting and correcting code associated with said received data record, said generated memory address and said received data record with said generated multi-bit error detecting and correcting code to determine whether errors are contained in said generated memory address and said received data record.
Claim 12
Dependent Claim
37 words
The method of claim 9 further comprising the step of: generating an error indication signal indicative of a failure of said generated memory address and received data record to match said generated error detecting and correcting code.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-04-03 | 1998-10-03 | 1999-04-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-04-03 | 2002-10-03 | 2003-04-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-04-03 | 2006-10-03 | 2007-04-04 | $7700.00 | Window Closed / Lapsed |