Instruction counter with sequential address checking means

Claim 1

IN A BINARY COUNTER OF THE TYPE HAVING FIRST AND SECOND NUMBER STORAGE REGISTERS AND AN ARITHMETIC ELEMENT OPERATIVE IN EACH OF A PLURALITY OF CYCLES TO ADD ONE TO THE CONTENT OF SAID FIRST REGISTER AND ENTER THE RESULT IN SAID SECOND REGISTER, THE IMPROVEMENT COMPRISING: MEANS FOR GENERATING THE PARITY OF THE NUMBER IN SAID SECOND REGISTER; MEANS FOR TRANSFERRING THE NUMBER IN SAID SECOND REGISTER TO SAID FIRST REGISTER; MEANS FOR STORING THE PARITY OF THE NUMBER TRANSFERRED TO SAID FIRST REGISTER; MEANS FOR COMPARING THE PARITY OF THE NUMBER IN SAID FIRST REGISTER WITH THE PARITY OF THE NEXT NUMBER ENTERED INTO SAID SECOND REGISTER BY SAID ARITHMETIC ELEMENT; MEANS FOR COMPARING THE NEXT NUMBER IN SAID SECOND REGISTER WITH THE NUMBER IN SAID FIRST REGISTER; AND MEANS RESPONSIVE TO SAID PARITY COMPARING MEANS AND SAID NUMBER COMPARING MEANS FOR INDICATING THAT THE NUMBER IN SAID SECOND REGISTER IS NOT GREATER THAN THE NUMBER IN SAID FIRST REGISTER BY A VOLUME OF ONE.