Semiconductor wafer probing method including arranging index regions that include all chips and minimize the occurrence of non-contact between a chip and a probe needle during chip verification

Claim 2

A semiconductor wafer probing method for contacting a plurality of probe needles of a probe card to a plurality of electrode pads of a plurality of chips on a semiconductor wafer so as to verify electrical characteristics of the chips, said method comprising the steps of: preparing a multi-probe card having a first plurality of probe needles corresponding to a first plurality of chips that are disposed in such a manner that an even number of chips are successively arranged in both row and column directions, the number of chips in at least one of the row and column directions being at least four; assigning as one index region, a region corresponding to a portion of the wafer wherein all the chips of the first plurality of chips can be verified by the multi-probe card at the same time; arranging a second plurality of the index regions so that the second plurality of index regions cover all the chips on the semiconductor wafer, and minimize the number of times the probe needles would not contact with a chip during verification of all chips corresponding to all index regions; defining a contact region made up of all of the index regions; and successively transferring the semiconductor wafer for contact between the probe needles and the electrode pad of each chip corresponding to each index region of the contact region.

Claim 3

The semiconductor wafer probing method as set forth in claim 1, wherein said transferring step includes transferring the semiconductor wafer from a first index region to a last index region in a shortest path.

Claim 4

A semiconductor wafer probing method for contacting a plurality of probe needles of a probe card to a plurality of electrode pads of a plurality of chips on a semiconductor wafer at the same time so as to verify electric characteristics of the chips, comprising the steps of: preparing a multi-probe card having a first plurality of probe needles corresponding to a first plurality of chips that are disposed in such a manner that an even number of chips are successively arranged in both row and column directions, the number of chips in at least one of the row and column directions being at least four; causing a display unit of a computer to display the semiconductor wafer and all the chips; assigning as one index region, on the display unit, a region where all of the first plurality of chips can be verified by the multi-probe card at the same time; arranging a second plurality of the index regions so that the index regions cover all the chips on the semiconductor wafer, and minimize the number of times the probe needles would not contact with a chip during verification of all chips corresponding to all index regions; defining a contact region on the display unit, the contact region being made up of all the index regions; and successively transferring the semiconductor wafer for contact between the probe needles and the electrode pad of each chip corresponding to each index region of the contact region.

Claim 5

A semiconductor wafer probing method for contacting a plurality of probe needles of a probe card to a plurality of electrode pads of a plurality of chips on a semiconductor wafer at the same time so as to verify electric characteristics of the chips, comprising the steps of: preparing a multi-probe card having a first plurality of probe needles corresponding to a first plurality of chips that are disposed in such a manner that an even number of chips are successively arranged in both row and column directions, the number of chips in at least one of the row and column directions being at least four; causing a display unit of a computer to display the semiconductor wafer and all the chips; assigning as one index region, on the display unit, a region where all of the first plurality of chips can be verified by the multi-probe card at the same time; arranging a second plurality of the index regions so that the index regions cover all the chips on the semiconductor wafer, and minimize the number of times the probe needles would not contact with a chip during verification of all chips corresponding to all index regions; defining a contact region on the display unit, the contact region being made up of all the index regions; and successively transferring the semiconductor wafer for contact between the probe needles and the electrode pad of each chip corresponding to each index region of the contact region.

Claim 6

The semiconductor wafer probing method as set forth in claim 3, wherein said transferring step includes transferring the semiconductor wafer to the contact region from a first index region to a last index region in a shortest path.

Claim 7

A semiconductor wafer probing method for contacting a plurality of probe needles of a probe card to a plurality of electrode pads of a plurality of chips on a semiconductor wafer so as to verify electrical characteristics of the chips, said method comprising the steps of: inputting semiconductor wafer information and chip information to a computer; inputting information of a multi-probe card having a first plurality of probe needles corresponding to a first plurality of chips to the computer; assigning as an index region, a region corresponding to a portion of the wafer wherein all of the chips of the first plurality of chips can be verified by the multi-probe card; displaying index regions on a display unit; using the computer to simulate a contact region defined by a second plurality of index regions that cover all of the chips on the semiconductor wafer; calculating the number of times the probe needles would not contact with a chip during verification of all the chips corresponding to all of the index regions; determining coordinates of the locations on the wafer where the probe needles would not contact with a chip from the results of the simulation and storing the results of the calculating step in the computer; and determining whether or not the number of transferring operations and the number of locations are proper based the information stored in the computer.

Claim 8

A semiconductor wafer probing method for contacting a plurality of probe needles of a probe card to a plurality of electrode pads of a plurality of chips on a semiconductor wafer so as to verify electrical characteristics of the chips, said method comprising the steps of: inputting semiconductor wafer information and chip information to a computer; inputting information of a multi-probe card having a first plurality of probe needles corresponding to a first plurality of chips to the computer; assigning as an index region, a region corresponding to a portion of the wafer wherein all of the chips of the first plurality of chips can be verified by the multi-probe card; displaying index regions on a display unit; using the computer to simulate a contact region defined by a second plurality of index regions that cover all of the chips on the semiconductor wafer; calculating the number of times the probe needles would not contact with a chip during verification of all the chips corresponding to all of the index regions; determining coordinates of the locations on the wafer where the probe needles would not contact with a chip from the results of the simulation and storing the results of the calculating step in the computer; and determining whether or not the number of transferring operations and the number of locations are proper based the information stored in the computer.

Claim 9

The semiconductor wafer probing method as set forth in claim 5, wherein said simulating step includes automatically assigning the index regions corresponding to a predetermined rule.

Claim 10

The semiconductor wafer probing method as set forth in claim 5, wherein said simulating step includes optimally assigning the index regions so that the number of index regions becomes minimum.

Claim 11

The semiconductor wafer probing method as set forth in claim 5, wherein said simulating step includes freely assigning the index regions.

Claim 12

The semiconductor wafer probing method as set forth in claim 6, wherein said automatically assigning step includes assigning the index regions so that the number of locations at one edge of a plurality of index regions disposed in a row becomes almost the same as that at the other edge thereof.

Claim 13

The semiconductor wafer probing method as set forth in claim 6, wherein said optimally assigning step includes assigning the index regions so that the number of locations at each of both edges of a plurality of index regions disposed in a row becomes minimum.