US4985676A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method and apparatus of performing probing test for electrically and sequentially testing semiconductor device patterns
Assignee: Tokyo Electron Ltd
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Filing: 1989-02-17
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Granted: 1991-01-15
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Expires: 2009-02-17
Abstract
Abstract This invention relates to a method and apparatus for performing a probing test for sequentially testing chips formed on a semiconductor wafer in a matrix form. An area of a chip subjected to the test or a chip excluded from the test on the wafer is preset, the preset-area information is stored, and only chips subjected to to the test are tested on the basis of the sequentially readout preset-area information.
Inventors
- 👤 Wataru Karasawa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 14:47
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/282; G01R31/2831; G01R31/2851; G01R31/2886; G01R31/2887; H; H10; H10W; H10W46/00; H10W46/501; H10W46/507
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
203 words
a method of performing a probing test for electrically and sequentially testing a plurality of chips formed in a matrix pattern upon a semiconductor wafer, comprising the steps of: (1) storing map information in a storing means, which is an area map distinguishing chip area from non-chip area in accordance with types of the wafer, and includes the address data of monitor chips in the chip area and also the address data of the end chips in a matrix form; (2) detecting a central point of the semiconductor wafer to insure the wafer is properly aligned with a probing means; (3) reading out the map information from the storing means in accordance with types of the wafer; (4) pre-aligning the wafer in an X-Y plane with reference to the probing means on the basis of the map information and the detected central point of the wafer; (5) sequentially testing said plurality of chips one by one by starting at one corner of the matrix pattern, and at one end of a first row of chips, and proceeding in a direction across the row; and (6) testing a next row of chips by beginning at an opposite end and proceeding in an opposite direction.
Claim 2
Independent Claim
203 words
a method of performing a probing test for electrically and sequentially testing a plurality of chips formed in a matrix pattern upon a semiconductor wafer, comprising the steps of: (1) storing map information in a storing means, which is an area map distinguishing chip area from non-chip area in accordance with types of the wafer, and includes the address data of monitor chips in the chip area and also the address data of the end chips in a matrix form; (2) detecting a central point of the semiconductor wafer to insure the wafer is properly aligned with a probing means; (3) reading out the map information from the storing means in accordance with types of the wafer; (4) pre-aligning the wafer in an X-Y plane with reference to the probing means on the basis of the map information and the detected central point of the wafer; (5) sequentially testing said plurality of chips one by one by starting at one corner of the matrix pattern, and at one end of a first row of chips, and proceeding in a direction across the row; and (6) testing a next row of chips by beginning at an opposite end and proceeding in an opposite direction.
Claim 3
Dependent Claim
17 words
A method according to claim 1, wherein: said plurality of chips are identical in area and shape.
Claim 4
Dependent Claim
16 words
A method according to claim 2, wherein: each of said plurality of chips is a square.
Claim 5
Dependent Claim
14 words
A method according to claim 1, wherein: the storing means includes a floppy disc.
Claim 6
Dependent Claim
48 words
A method according to claim 1, wherein: the arrangement of chips on the wafer is imaged by a television camera and displayed on a monitor, the storing means giving addresses to the plurality of chips corresponding to column numbers for the X-axis and row numbers for the Y-axis.
Claim 7
Dependent Claim
22 words
A method according to claim 1, wherein: the chips subjected to the probing test are printed on the wafer with a stepper.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-01-14 | 1994-07-16 | 1995-01-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-01-14 | 1998-07-16 | 1999-01-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-01-14 | 2002-07-16 | 2003-01-15 | $7700.00 | Window Closed / Lapsed |