US5585308A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method for improved pre-metal planarization
Assignee: STMicroelectronics lnc USA
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Filing: 1995-03-29
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Granted: 1996-12-17
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Expires: 2015-03-29
Abstract
Abstract A method of forming an integrated circuit wherein a planarization step is been performed before the primary metal deposition step, but after deposition of the adhesion and barrier layers. Thus the adhesion and barrier layers are present on the sidewalls of contact holes, but do not underlie the whole extent of the primary metallization.
Inventors
- 👤 John C. Sardella
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 04:36
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/071; H10W20/092; Y; Y10; Y10S; Y10S257/00; Y10S257/915
Claims Analysis
Total Claims: 38
Claim 1
Independent Claim
150 words
A method for fabricating integrated circuits, comprising the steps of: (a.) providing a partially fabricated structure which includes transistors; (b.) depositing an interlevel dielectric layer over said transistors; (c.) etching contact holes into said interlevel dielectric layer, to expose portions of said transistors for electrical connection; (d.) depositing a first conductive layer over said interlevel dielectric layer, and on the bottoms of said contact holes; (e.) depositing a planar sacrificial material, and nonselectively etching away all of said sacrificial material except in said contact holes; said etch being continued for long enough to completely remove said first conductive layer from, and to planarize, at least some portions of said interlevel dielectric; and thereafter selectively etching away said sacrificial material from said contact holes; and (f.) depositing an additional layer of metal, which is thicker than said first conductive layer, and patterning said metal to form electrical interconnections among said transistors.
Claim 2
Independent Claim
150 words
A method for fabricating integrated circuits, comprising the steps of: (a.) providing a partially fabricated structure which includes transistors; (b.) depositing an interlevel dielectric layer over said transistors; (c.) etching contact holes into said interlevel dielectric layer, to expose portions of said transistors for electrical connection; (d.) depositing a first conductive layer over said interlevel dielectric layer, and on the bottoms of said contact holes; (e.) depositing a planar sacrificial material, and nonselectively etching away all of said sacrificial material except in said contact holes; said etch being continued for long enough to completely remove said first conductive layer from, and to planarize, at least some portions of said interlevel dielectric; and thereafter selectively etching away said sacrificial material from said contact holes; and (f.) depositing an additional layer of metal, which is thicker than said first conductive layer, and patterning said metal to form electrical interconnections among said transistors.
Claim 3
Dependent Claim
13 words
The method of claim 1, wherein said first conductive layer comprises titanium nitride.
Claim 4
Dependent Claim
19 words
The method of claim 1, wherein said interlevel dielectric comprises a doped silicate glass over an undoped silicate glass.
Claim 5
Dependent Claim
12 words
The method of claim 1, wherein said interlevel dielectric comprises borophosphosilicate glass.
Claim 6
Dependent Claim
27 words
The method of claim 1, wherein said additional metal layer is deposited to a thickness in the range between about 3000 Å and about 8000 Å inclusive.
Claim 7
Dependent Claim
16 words
The method of claim 1, wherein said additional metal layer consists of an alloy of aluminum.
Claim 8
Dependent Claim
28 words
The method of claim 1, wherein said additional metal layer comprises an alloy of aluminum over a second conductive layer comprising at least 40% by weight of titanium.
Claim 9
Dependent Claim
14 words
The method of claim 1, wherein said additional metal layer comprises a multilayer structure.
Claim 10
Dependent Claim
20 words
The method of claim 1, wherein said interlevel dielectric has a total thickness in the range of 3000-10,000 Å inclusive.
Claim 11
Dependent Claim
22 words
The method of claim 1, wherein said first conductive layer is deposited uniformly on the bottoms and sidewalls of said contact holes.
Claim 12
Independent Claim
150 words
A method for fabricating integrated circuits, comprising the steps of: (a.) providing a partially fabricated structure which includes transistors; (b.) depositing an interlevel dielectric layer over said transistors; (c.) etching contact holes into said interlevel dielectric layer, to expose portions of said transistors for electrical connection; (d.) depositing first and second conductive layers over said interlevel dielectric layer, and on the bottoms of said contact holes; (e.) performing planarization by depositing a planar sacrificial material and non-selectively etching to a depth sufficient to completely remove said first conductive layer from at least some portions of said interlevel dielectric and to remove at least some portions of said interlevel dielectric; (f). selectively etching away said sacrificial material from said contact holes; and (g.) depositing an additional layer of metal, which is thicker than said first and said second conductive layers, and patterning said metal to form electrical interconnections among said transistors.
Claim 13
Independent Claim
150 words
A method for fabricating integrated circuits, comprising the steps of: (a.) providing a partially fabricated structure which includes transistors; (b.) depositing an interlevel dielectric layer over said transistors; (c.) etching contact holes into said interlevel dielectric layer, to expose portions of said transistors for electrical connection; (d.) depositing first and second conductive layers over said interlevel dielectric layer, and on the bottoms of said contact holes; (e.) performing planarization by depositing a planar sacrificial material and non-selectively etching to a depth sufficient to completely remove said first conductive layer from at least some portions of said interlevel dielectric and to remove at least some portions of said interlevel dielectric; (f). selectively etching away said sacrificial material from said contact holes; and (g.) depositing an additional layer of metal, which is thicker than said first and said second conductive layers, and patterning said metal to form electrical interconnections among said transistors.
Claim 14
Dependent Claim
13 words
The method of claim 11, wherein said first conductive layer comprises titanium nitride.
Claim 15
Dependent Claim
21 words
The method of claim 11, wherein said first conductive layer comprises metallic titanium, and said second conductive layer comprises titanium nitride.
Claim 16
Dependent Claim
24 words
The method of claim 11, wherein said first and second conductive layers are deposited uniformly on the bottoms and sidewalls of said contact holes.
Claim 17
Dependent Claim
14 words
The method of claim 11, wherein said first conductive layer comprises a layered structure.
Claim 18
Dependent Claim
15 words
The method of claim 11, wherein said first conductive layer comprises a Ti/TiN layered structure.
Claim 19
Dependent Claim
19 words
The method of claim 11, wherein said interlevel dielectric comprises a doped silicate glass over an undoped silicate glass.
Claim 20
Dependent Claim
12 words
The method of claim 11, wherein said interlevel dielectric comprises borophosphosilicate glass.
Claim 21
Dependent Claim
27 words
The method of claim 11, wherein said additional metal layer is deposited to a thickness in the range between about 3000 Å and about 8000 Å inclusive.
Claim 22
Dependent Claim
16 words
The method of claim 11, wherein said additional metal layer consists of an alloy of aluminum.
Claim 23
Dependent Claim
30 words
The method of claim 11, wherein said additional metal layer comprises an alloy of aluminum over said second conductive layer, which comprises at least 40 atomic weight % of titanium.
Claim 24
Dependent Claim
14 words
The method of claim 11, wherein said additional metal layer comprises a multilayer structure.
Claim 25
Dependent Claim
20 words
The method of claim 11, wherein said interlevel dielectric has a total thickness in the range of 3000-10,000 Å inclusive.
Claim 26
Independent Claim
132 words
A method for fabricating integrated circuits, comprising the steps of: (a.) providing a partially fabricated structure which includes transistors; (b.) depositing an interlevel dielectric layer over said transistors; (c.) etching contact holes into said interlevel dielectric layer, to expose portions of said transistors for electrical connection; (d.) depositing a first conductive layer over said interlevel dielectric layer, and on the bottoms of said contact holes; (e.) performing planarization to a depth sufficient to completely remove said first conductive layer from at least some portions of said interlevel dielectric and to remove at least some portions of said interlevel dielectric; (f.) after the planarization step, depositing and patterning an additional layer of metal, which is thicker than said first conductive layer, to fill said holes and to form electrical interconnections among said transistors.
Claim 27
Independent Claim
132 words
A method for fabricating integrated circuits, comprising the steps of: (a.) providing a partially fabricated structure which includes transistors; (b.) depositing an interlevel dielectric layer over said transistors; (c.) etching contact holes into said interlevel dielectric layer, to expose portions of said transistors for electrical connection; (d.) depositing a first conductive layer over said interlevel dielectric layer, and on the bottoms of said contact holes; (e.) performing planarization to a depth sufficient to completely remove said first conductive layer from at least some portions of said interlevel dielectric and to remove at least some portions of said interlevel dielectric; (f.) after the planarization step, depositing and patterning an additional layer of metal, which is thicker than said first conductive layer, to fill said holes and to form electrical interconnections among said transistors.
Claim 28
Dependent Claim
13 words
The method of claim 24, wherein said first conductive layer comprises titanium nitride.
Claim 29
Dependent Claim
14 words
The method of claim 24, wherein said first conductive layer comprises a layered structure.
Claim 30
Dependent Claim
15 words
The method of claim 24, wherein said first conductive layer comprises a Ti/TiN layered structure.
Claim 31
Dependent Claim
19 words
The method of claim 24, wherein said interlevel dielectric comprises a doped silicate glass over an undoped silicate glass.
Claim 32
Dependent Claim
12 words
The method of claim 24, wherein said interlevel dielectric comprises borophosphosilicate glass.
Claim 33
Dependent Claim
27 words
The method of claim 24, wherein said additional metal layer is deposited to a thickness in the range between about 3000 Å and about 8000 Å inclusive.
Claim 34
Dependent Claim
16 words
The method of claim 24, wherein said additional metal layer consists of an alloy of aluminum.
Claim 35
Dependent Claim
29 words
The method of claim 24, wherein said additional metal layer comprises an alloy of aluminum over a second conductive layer comprising at least 40 atomic weight % of titanium.
Claim 36
Dependent Claim
14 words
The method of claim 24, wherein said additional metal layer comprises a multilayer structure.
Claim 37
Dependent Claim
20 words
The method of claim 24, wherein said interlevel dielectric has a total thickness in the range of 3000-10,000 Å inclusive.
Claim 38
Dependent Claim
22 words
The method of claim 34, wherein said first conductive layer is deposited uniformly on the bottoms and sidewalls of said contact holes.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-12-17 | 2000-06-17 | 2000-12-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-12-17 | 2004-06-17 | 2004-12-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-12-17 | 2008-06-17 | 2008-12-17 | $7700.00 | Window Closed / Lapsed |