US5585295A
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Method for forming inverse-T gate lightly-doped drain (ITLDD) device
Assignee: Vanguard International Semiconductor Corp
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Filing: 1996-03-29
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Granted: 1996-12-17
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Expires: 2016-03-29
Abstract
Abstract A method for forming an inverse-T gate lightly-doped drain (ITLDD) structure for deep sub-micron metal oxide semiconductor (MOS) transistors is disclosed. The present invention includes forming a gate oxide layer on a substrate, and forming stacked-amorphous-silicon layers on the gate oxide layer, where the stacked-amorphous-silicon layers comprise at least two layers. Next, a first dielectric layer is patterned on top of the stacked-amorphous-silicon layer by a photoresist mask, and then a lightly-doped source/drain regions is formed. Thereafter, all of the stacked-amorphous-silicon layers are removed except for the bottom amorphous polysilicon layer. A second dielectric spacer is formed on the sidewalls of the stacked-amorphous-silicon layers and heavily-doped source/drain regions are formed. The bottom layer of the stacked-amorphous-silicon layers is and the gate oxide layer is removed using the spacer as an etch mask. The first dielectric layer and the second dielectric spacer is removed and a third dielectric spacer is formed on the sidewalls of the stacked-amorphous-silicon layers and the gate oxide layer. Finally, a silicide is formed on top of the stacked-amorphous-silicon layers and on portions of the heavily-doped source/drain regions.
Inventors
- 👤 Shye-Lin Wu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 08:02
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D30/0227; H10D30/0212; H10D30/60; H10D30/601; H10D30/605; H10D64/00; H10D64/01; H10D64/013; H10D64/01302; H10D64/01304; H10D64/01306; H10D64/01308; H10D64/0131; H10D64/01324; H10D64/20; H10D64/27; H10D64/311; H10D64/411; H10D64/511; H10D64/517; H10D64/518; H10D64/60; H10D64/66
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
173 words
A method for forming an inverse-T gate lightly-doped drain (ITLDD) device, said method comprising: forming a gate oxide layer on a substrate; forming stacked-amorphous-silicon layers on the gate oxide layer, said stacked-amorphous-silicon layers comprising at least two layers; patterning a first dielectric layer on top of the stacked-amorphous-silicon layers by a photoresist mask; forming lightly-doped source/drain regions using said photoresist mask; removing portions of the stacked-amorphous-silicon layers until the bottom layer of said stacked-amorphous-silicon layers is exposed using said photoresist mask; forming a second dielectric spacer on the sidewalls of the stacked-amorphous-silicon layers; forming heavily-doped source/drain regions, said first dielectric layer and said second dielectric spacer serve as an implant mask; removing the bottom layer of said stacked-amorphous-silicon layers, and the gate oxide layer using said implant mask; removing the first dielectric layer and the second dielectric spacer; forming a third dielectric spacer on the sidewalls of the stacked-amorphous-silicon layers and the gate oxide layer; and forming a silicide on top of the stacked-amorphous-silicon layers and on portions of the heavily-doped source/drain regions.
Claim 2
Independent Claim
173 words
A method for forming an inverse-T gate lightly-doped drain (ITLDD) device, said method comprising: forming a gate oxide layer on a substrate; forming stacked-amorphous-silicon layers on the gate oxide layer, said stacked-amorphous-silicon layers comprising at least two layers; patterning a first dielectric layer on top of the stacked-amorphous-silicon layers by a photoresist mask; forming lightly-doped source/drain regions using said photoresist mask; removing portions of the stacked-amorphous-silicon layers until the bottom layer of said stacked-amorphous-silicon layers is exposed using said photoresist mask; forming a second dielectric spacer on the sidewalls of the stacked-amorphous-silicon layers; forming heavily-doped source/drain regions, said first dielectric layer and said second dielectric spacer serve as an implant mask; removing the bottom layer of said stacked-amorphous-silicon layers, and the gate oxide layer using said implant mask; removing the first dielectric layer and the second dielectric spacer; forming a third dielectric spacer on the sidewalls of the stacked-amorphous-silicon layers and the gate oxide layer; and forming a silicide on top of the stacked-amorphous-silicon layers and on portions of the heavily-doped source/drain regions.
Claim 3
Dependent Claim
17 words
The method according to claim 1, wherein said first dielectric layer is a first silicon nitride layer.
Claim 4
Dependent Claim
17 words
The method according to claim 1, wherein said lightly-doped source/drain regions are formed using an ion-implant method.
Claim 5
Dependent Claim
51 words
The method according to claim 1, wherein the step of forming the second dielectric spacer comprises the steps of: forming the second dielectric layer on the first dielectric layer and the bottom layer of the stacked-amorphous-silicon layers; and etching back said second dielectric layer anisotropically to form said second dielectric spacer.
Claim 6
Dependent Claim
17 words
The method according to claim 1, wherein said second dielectric spacer is a second silicon nitride spacer.
Claim 7
Dependent Claim
19 words
The method according to claim 5, wherein said second dielectric spacer is formed using a reactive ion etch method.
Claim 8
Dependent Claim
17 words
The method according to claim 1, wherein said heavily-doped source/drain regions are formed using an ion-implant method.
Claim 9
Dependent Claim
16 words
The method according to claim 1, further including the step of annealing the heavily-doped source/drain regions.
Claim 10
Dependent Claim
16 words
The method according to claim 8, wherein said heavily-doped source/drain regions are annealed using a furnace.
Claim 11
Dependent Claim
18 words
The method according to claim 8, wherein said heavily-doped source/drain regions are annealed using a rapid thermal process.
Claim 12
Dependent Claim
60 words
The method according to claim 1, wherein the step of forming the third dielectric spacer comprises the steps of: forming the third dielectric layer on top of the stacked-amorphous-silicon layers, portions of the bottom layer of the stacked-amorphous-silicon layers, and portions of the heavily-doped source/drain regions; and etching back said third dielectric layer anisotropically to form said third dielectric spacer.
Claim 13
Dependent Claim
17 words
The method according to claim 1, wherein said third dielectric spacer is a third silicon nitride spacer.
Claim 14
Dependent Claim
19 words
The method according to claim 12, wherein said third dielectric spacer is formed using the reactive ion etch method.
Claim 15
Dependent Claim
24 words
The method according to claim 1, wherein the length at the bottom of said second dielectric spacer is in the range of 0.25˜0.30 micrometer.
Claim 16
Dependent Claim
18 words
The method according to claim 1, wherein a phosphorus dopant is used to form said lightly-doped source/drain regions.
Claim 17
Dependent Claim
18 words
The method according to claim 1, wherein an arsenic dopant is used to formed said heavily-doped source/drain regions.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-12-17 | 2000-06-17 | 2000-12-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-12-17 | 2004-06-17 | 2004-12-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-12-17 | 2008-06-17 | 2008-12-17 | $7700.00 | Window Closed / Lapsed |